I.MX27 datasheet(76/152 Pages) FREESCALE

Part #	I.MX27

Description	Multimedia Applications Processor Multiple clock and power domains

PDF	152 Pages

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Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

Direct Link	http://www.freescale.com

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i.MX27 and i.MX27L Data Sheet, Rev. 1.7

Freescale Semiconductor

Electrical Characteristics

NOTE

SDR SDRAM CLK parameters are being measured from the 50%

point—that is, high is defined as 50% of signal value and low is defined as

50% of signal value.

The timing parameters are similar to the ones used in SDRAM data

sheets—that is, Table 38 indicates SDRAM requirements. All output signals

are driven by the ESDCTL at the negative edge of SDCLK and the

parameters are measured at maximum memory frequency.

Figure 39. SDRAM Refresh Timing Diagram

SD13

Data setup time

tDS

2.0

—

SD14

Data hold time

tDH

1.3

—

Note:

1 SD11 and SD12 are determined by SDRAM controller register settings.

Table 39. SDRAM Refresh Timing Parameters

Parameter

Symbol

Min

Max

Unit

SD1

SDRAM clock high-level width

tCH

3.4

4.1

SD2

SDRAM clock low-level width

tCL

3.4

4.1

Table 38. SDR SDRAM Write Timing Parameters (continued)

Parameter

Symbol

Min

Max

Unit

CAS

RAS

ADDR

ROW/BA

SD6

SD7

SD11

SD10

SDCLK

SD1

SD2

SDCLK

SD3

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