MM912G634CV2AP datasheet(97/345 Pages) FREESCALE

97 / 345 page

PWM Control Module (PWM8B2C)

MM912_634 Advance Information, Rev. 4.0

Freescale Semiconductor

NOTE

Changing the PWM output mode from left aligned to center aligned output (or vice versa)

while channels are operating can cause irregularities in the PWM output. It is recommended

to program the output mode before enabling the PWM channel.

Figure 25. PWM Left Aligned Output Waveform

To calculate the output frequency in left aligned output mode for a particular channel, take the selected clock source frequency

for the channel (A, B, SA, or SB), and divide it by the value in the period register for that channel.

•

PWMx Frequency = Clock (A, B, SA, or SB) / PWMPERx

•

PWMx Duty Cycle (high time as a % of period):

—

Polarity = 0 (PPOLx = 0)

•

Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%

—

Polarity = 1 (PPOLx = 1)

Duty Cycle = [PWMDTYx / PWMPERx] * 100%

As an example of a left aligned output, consider the following case:

Clock Source = E, where E = 10 kHz (100 µs period)

PPOLx = 0

PWMPERx = 4

PWMDTYx = 1

PWMx Frequency = 10 kHz/4 = 2.5 kHz

PWMx Period = 400 µs

PWMx Duty Cycle = 3/4 *100% = 75%

The output waveform generated is shown in Figure 26.

Figure 26. PWM Left Aligned Output Example Waveform

4.14.4.2.6

Center Aligned Outputs

For a center aligned output mode selection, set the CAEx bit (CAEx = 1) in the PWMCTL register, and the corresponding PWM

output will be center aligned.

The 8-bit counter operates as an up/down counter in this mode, and is set to up whenever the counter is equal to $00. The counter

compares to two registers, a duty register and a period register, as shown in the block diagram in Figure 24. When the PWM

counter matches the duty register, the output flip-flop changes state, causing the PWM waveform to also change state. A match

between the PWM counter and the period register changes the counter direction from an up-count to a down-count. When the

PWM counter decrements and matches the duty register again, the output flip-flop changes state, causing the PWM output to

also change state. When the PWM counter decrements and reaches zero, the counter direction changes from a down-count back

to an up-count, and a load from the double buffer period and duty registers to the associated registers is performed, as described

PWMDTYx

Period = PWMPERx

PPOLx = 0

PPOLx = 1

Period = 400 µs

E=100µs

Duty Cycle = 75%

MM912G634CV2AP Datasheet(PDF) 97 Page - Freescale Semiconductor, Inc

MM912G634CV2AP Datasheet(HTML) 97 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL