SC16IS740IPW datasheet(13/63 Pages) NXP

13 / 63 page

SC16IS740_750_760

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Product data sheet

Rev. 7 — 9 June 2011

13 of 63

NXP Semiconductors

SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

7.4 Reset and power-on sequence

7.4.1 Hardware reset, Power-On Reset (POR) and software reset

These three reset methods are identical and will reset the internal registers as indicated in

Table 4.

Table 4 summarizes the state of register.

Fig 11. Example of software flow control

TRANSMIT FIFO

PARALLEL-TO-SERIAL

SERIAL-TO-PARALLEL

Xon1 WORD

Xon2 WORD

Xoff1 WORD

Xoff2 WORD

RECEIVE FIFO

PARALLEL-TO-SERIAL

SERIAL-TO-PARALLEL

Xon1 WORD

Xon2 WORD

Xoff1 WORD

Xoff2 WORD

UART2

UART1

002aaa229

data

Xoff–Xon–Xoff

compare

programmed

Xon-Xoff

characters

Table 4.

Reset state

Interrupt Enable Register

all bits cleared

Interrupt Identification Register

bit 0 is set; all other bits cleared

FIFO Control Register

all bits cleared

Line Control Register

reset to 0001 1101 (0x1D)

Modem Control Register

all bits cleared

Line Status Register

bit 5 and bit 6 set; all other bits cleared

Modem Status Register

bits 0:3 cleared; bits 4:7 input signals

Enhanced Feature Register

all bits cleared

Receiver Holding Register

pointer logic cleared

Transmitter Holding Register

pointer logic cleared

Transmission Control Register

all bits cleared.

Trigger Level Register

all bits cleared.

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