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TLE6270R Datasheet(PDF) 21 Page - Infineon Technologies AG |
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TLE6270R Datasheet(HTML) 21 Page - Infineon Technologies AG |
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21 / 35 page ![]() Data Sheet 21 V1.3, 2008-12-23 TLE6270R Quad Low Side Injector Driver Functional Description 5.5 Protections 5.5.1 All Inputs/Outputs All pins are protected against ESD 2kV Human body model. 5.5.2 T1, T4 Power Transistors • Protection against damaging failures Note: The protection latches are reset when the NON input is at high level. • Protection against overvoltage A clamping circuit limits the output voltage to a defined value ( V clp) in order to avoid the breakdown of the output transistor when the solenoid load is switched off. • Protection against turn on due to fast voltage ramp on output. A very fast voltage slope on the output can turn on the power transistor (capacitive effects) especially when the normal gate pull-down structure is not active (IC not supplied, V CC too low …). In this case, the transistor is turned off immediately. This function is guaranteed for V CC between 0 and 5.5 V. 5.6 Reset There are two different reset functions: • Undervoltage reset • NRES reset pin If one or several of the following conditions are present: • V CC lower than VCCRES, • NRES pin at low level, the low side T1, T4 are switched off, NCTL2 and NCTL3 set to high level, all diagnostic registers are reset and the SDO is tri-stated. Table 5 Protection against Damaging Failures Problem detected Transistors switched off T1 or T4 overcurrent T1, T4 (internally) and T2, T3 (via NCTL2, NCTL3) T1 or T4 overtemperature T1, T4 (internally) and T2, T3 (via NCTL2, NCTL3) HS_Diag L → H T1, T4 (internally) and T2, T3 (via NCTL2, NCTL3) T1 or T4 peak current undertime T1, T4 (internally) and T2, T3 (via NCTL2, NCTL3) T1 or T4 peak current overtime T1, T4 (internally) and T2, T3 (via NCTL2, NCTL3) and t 2 starts. |
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