TLE42754D datasheet(9/26 Pages) INFINEON

9 / 26 page

Data Sheet

Rev. 1.1, 2008-09-24

TLE42754

General Product Characteristics

4.3

Thermal Resistance

Pos.

Parameter

Symbol

Limit Value

Unit

Conditions

Min.

Typ.

Max.

TLE42754D (PG-TO252-5)

4.3.4

Junction to Case1)

1) not subject to production test, specified by design

thJC

–3.7

–K/W

–

4.3.5

Junction to Ambient1)

thJA

–27

–

K/W

2) Specified

thJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product

(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).

Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.

4.3.6

–

110

–

K/W

footprint only3)

3) Specified

thJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product

(Chip+Package) was simulated on a 76.2

× 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu).

4.3.7

–

K/W

300 mm2 heatsink area

on PCB3)

4.3.8

–

K/W

600 mm2 heatsink area

on PCB3)

TLE42754G (PG-TO263-5)

4.3.9

Junction to Case1)

thJC

–3.7

–K/W

–

4.3.10

Junction to Ambient1)

thJA

–22

–

K/W

4.3.11

–

K/W

footprint only3)

4.3.12

–

K/W

300 mm2 heatsink area

on PCB3)

4.3.13

–

K/W

600 mm2 heatsink area

on PCB3)

TLE42754E (PG-SSOP-14 exposed pad)

4.3.14

Junction to Case1)

thJC

–7–K/W

–

4.3.15

Junction to Ambient1)

thJA

–43

–

K/W

4.3.16

–

120

–

K/W

footprint only3)

4.3.17

–

K/W

300 mm2 heatsink area

on PCB3)

4.3.18

–

K/W

600 mm2 heatsink area

on PCB3)

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