LTC2990CMSTRPBF datasheet(12/24 Pages) LINER

12 / 24 page

LTC2990

2990f

applicaTions inForMaTion

where RSENSE is the current sensing resistor, typically

<1Ω.

VCC:TheLTC2990measuresVCC.Toconvertthecontentsof

the VCC register to voltage, use the following equation:

VCC = 2.5 + D[13:0] • 305.18µV

Digital Interface

The LTC2990 communicates with a bus master using a

two-wire interface compatible with the I2C Bus and the

SMBus, an I2C extension for low power devices.

The LTC2990 is a read-write slave device and supports

SMBusbusReadByteDataandWriteByteData,ReadWord

Data and Write Word Data commands. The data formats

for these commands are shown in Tables 2 though 9.

The connected devices can only pull the bus wires LOW

and can never drive the bus HIGH. The bus wires are

externally connected to a positive supply voltage via a

current source or pull-up resistor. When the bus is free,

both lines are HIGH. Data on the I2C bus can be transferred

at rates of up to 100kbit/s in the standard mode and up to

400kbit/s in the fast mode. Each device on the I2C bus is

recognized by a unique address stored in that device and

can operate as either a transmitter or receiver, depending

on the function of the device. In addition to transmitters

and receivers, devices can also be considered as masters

or slaves when performing data transfers. A master is

the device which initiates a data transfer on the bus and

generates the clock signals to permit that transfer. At the

same time any device addressed is considered a slave.

The LTC2990 can only be addressed as a slave. Once ad-

dressed, it can receive configuration bits or transmit the

last conversion result. Therefore the serial clock line SCL

is an input only and the data line SDA is bidirectional. The

device supports the standard mode and the fast mode for

data transfer speeds up to 400kbit/s. The Timing Diagram

shows the definition of timing for fast/standard mode

devices on the I2C bus.

The internal state machine cannot

updateinternaldataregistersduringanI2Creadoperation.

The state machine pauses until the I2C read is complete.

It is therefore, important not to leave the LTC2990 in this

state for long durations, or increased conversion latency

will be experienced.

START and STOP Conditions

When the bus is idle, both SCL and SDA must be high. A

bus master signals the beginning of a transmission with

a START condition by transitioning SDA from high to low

while SCL is high. When the bus is in use, it stays busy

if a repeated START (SR) is generated instead of a STOP

condition. The repeated START (SR) conditions are func-

tionally identical to the START (S). When the master has

finished communicating with the slave, it issues a STOP

condition by transitioning SDA from low to high while SCL

is high. The bus is then free for another transmission.

I2C Device Addressing

Four distinct bus addresses are configurable using the

ADR0-ADR1 pins. Table 1 shows the correspondence

between ADR0 and ADR1 pin states and addresses.

Acknowledge

The acknowledge signal is used for handshaking between

thetransmitterandthereceivertoindicatethatthelastbyte

of data was received. The transmitter always releases the

SDA line during the acknowledge clock pulse. When the

slave is the receiver, it must pull down the SDA line so that

it remains LOW during this pulse to acknowledge receipt

of the data. If the slave fails to acknowledge by leaving

SDA HIGH, then the master can abort the transmission by

generatingaSTOPcondition.Whenthemasterisreceiving

data from the slave, the master must pull down the SDA

line during the clock pulse to indicate receipt of the data.

After the last byte has been received the master will leave

the SDA line HIGH (not acknowledge) and issue a STOP

condition to terminate the transmission.

Write Protocol

The master begins communication with a START condi-

tion followed by the seven bit slave address and the R/W#

bit set to zero. The addressed LTC2990 acknowledges

the address and then the master sends a command byte

which indicates which internal register the master wishes

to write. The LTC2990 acknowledges the command byte

and then latches the lower four bits of the command byte

into its internal Register Address pointer. The master then

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