DS80C390 datasheet(49/53 Pages) DALLAS

49 / 53 page

DS80C390 Dual CAN High-Speed Microprocessor

49 of 53

CAN INTERRUPTS

The DS80C390 supports three interrupts associated with the CAN controllers. One interrupt is dedicated to each

CAN controller, providing receive/transmit acknowledgments from each of its 15 message centers. The remaining

interrupt, the CAN bus activity interrupt, is used to detect CAN bus activity on the C0RX or C1RX pins.

The message center interrupts are enabled/disabled by individual ETI (transmit) and ERI (receive) enable bits in

the corresponding message control register (located in SFR memory) for each message center. All the message

center interrupts of each CAN module are ORed together into their respective CAN interrupt. The successful

transmission or receipt of a message sets the INTRQ bit in the corresponding message control register (located in

SFR memory). This bit can only be cleared through software. In addition, the global interrupt-enable bit (IE.7) and

the specific CAN interrupt-enable bit, EIE.6 (CAN0) or EIE.5 (CAN1), must be correctly set to acknowledge a

message center interrupt.

Interrupt assertion of error and status conditions associated with the CAN modules is controlled by the ERIE and

STIE bits located in the CAN control registers, C0C and C1C.

ARBITRATION AND MASKING

After a CAN module has ascertained that an incoming message is bit-error-free, the identification field of that

message is then compared against one or more arbitration values to determine if they will be loaded into a

message center. Each enabled message center (see the MSRDY bit in the CAN Message Control Register) is

tested in order from 1 to 15. The first message center to successfully pass the test receives the incoming message

and ends the testing. Using masking registers allows the use of more complex identification schemes, as tests can

be made based on bit patterns rather than an exact match between all bits in the identification field and arbitration

values. Each CAN processor also incorporates a set of five masks to allow messages with different IDs to be

grouped and successfully loaded into a message center. Note that some of these masks are optional as per the

bits shown in the Arbitration/Masking Feature Summary table (Table 14).

There are several possible arbitration tests, varying according to which message center is involved. If all the

enabled tests succeed, the message is loaded into the respective message center. The most basic test, performed

on all messages, compares either 11 (CAN 2.0A) or 29 (CAN 2.0B) bits of the identification field to the appropriate

arbitration register, based on the EX/

ST bit in the CAN 0/1 format register. The MEME bit (C0MxF.1 or C1MxF.1)

controls whether the arbitration and ID registers are compared directly or through a mask register. A special set of

arbitration registers dedicated to message center 15 allows added flexibility in filtering this location.

If desired, further arbitration can be performed by comparing the first two bytes of the data field in each message

against two 8-bit media arbitration register bytes. The MDME bit in the CAN message center format registers

(C0MxF.0 or C1MxF.0) either disables (MDME = 0) arbitration, or enables (MDME = 1) arbitration using the media

ID mask registers 0–1.

If the 11-bit or 29-bit arbitration and the optional media-byte arbitration are successful, the message is loaded into

the respective message center. The format register also allows the microcontroller to program each message

center to function in a receive or transmit mode through the T/

R bit, and to use from 0 to 8 data bytes within the

data field of a message. Note that message center 15 can only be used in a receive mode. To avoid a priority

inversion, the DS80C390 CAN processors are configured to reload the transmit buffer with the message of the

highest priority (lowest message center number) whenever an arbitration is lost or an error condition occurs.

DS80C390 Datasheet(PDF) 49 Page - Dallas Semiconductor

DS80C390 Datasheet(HTML) 49 Page - Dallas Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

Datasheet Download

Link URL