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HMC983LP5E

v00.0911

DC - 7 GHZ FRACTIONAL-N DIVIDER

AND FREQUENCY SWEEPER

For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824

978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com

Application Support: apps@hittite.com

Figure 20. RF Input Stage

RF Path Fractional-N Divider

The RF input buffer is followed by a high frequency prescaler and a multi modulus divider. The divider has been

designed for the best output phase noise and spurious performance in both fractional and integer mode. The

(1048571) in fractional-N mode. The divider output pulse width depends on the RF input period and is adjustable via

SPI setting (refer to Duty Cycle Setting in register Reg 0Fh[14:12]). The output pulse width recommended setting is

40% to 60% where possible. At low output frequencies it may not be possible to set 50% duty cycle. In such cases the

maximum pulse width setting is recommended.

Figure 21. Divider Path

Divider Output Buffer

The divider output is differential and the output buffer stage is an open collector amplifier with off-chip pull-up resistors.

Due to sharp rise and fall times at the divider output, the external path should be designed differentially using RF

techniques.

When HMC983LP5E and HMC984LP4E are operating together as a frequency synthesizer, 50 Ω pull-up resistors are

provided in HMC984LP4E.

VPPBUF pin should be connected to 5 V power supply. This pin does not sink DC current and is only used to bias the

internal ESD diodes and to provide an appropriate voltage level for the phase detector chip (HMC984LP4E). The two

possible interface configurations are shown in Figure 22 and Figure 23 below.