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GS9062-CFE3 Datasheet(PDF) 26 Page - Gennum Corporation |
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GS9062-CFE3 Datasheet(HTML) 26 Page - Gennum Corporation |
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26 / 46 page ![]() GS9062 Data Sheet 22209 - 7 February 2007 26 of 46 3.5 Data-Through Mode The GS9062 may be configured by the application layer to operate as a simple parallel-to-serial converter. In this mode, the device presents data to the output buffer without performing any scrambling or encoding. Data-through mode is enabled only when both the SMPTE_BYPASS and DVB_ASI pins are set LOW. 3.6 Additional Processing Functions The GS9062 contains an additional data processing block which is available in SMPTE mode only, SMPTE Mode on page 23. 3.6.1 Input Data Blank The video input data may be 'blanked' by the GS9062. In this mode, all input video data except TRS words are set to the appropriate blanking levels by the device. Both the horizontal and vertical ancillary data spaces will also be set to blanking levels. This function is enabled by setting the BLANK pin LOW. 3.6.2 Automatic Video Standard Detection The GS9062 can detect the input video standard by using the timing parameters extracted from the received TRS ID words or supplied H, V, and F timing signals Internal Flywheel on page 23. This information is presented to the host interface via the VIDEO_STANDARD register (Table 3-2). Total samples per line, active samples per line, total lines per field/frame and active lines per field/frame are also calculated and presented to the host interface via the RASTER_STRUCTURE registers (Table 3-3). These line and sample count registers are updated once per frame at the end of line 12. This is in addition to the information contained in the VIDEO_STANDARD register. After device reset, the four RASTER_STRUCTURE registers default to zero. Table 3-2: Host Interface Description for Video Standard Register Register Name Bit Name Description R/W Default VIDEO_STANDARD Address: 04h 15 Not Used 14–10 VD_STD[4:0] Video Data Standard (see Table 3-4)R 0 9 Not Used 8 STD_LOCK Standard Lock: Set HIGH when flywheel has achieved full synchronization. R0 7–0 Not Used |
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