HT16L21 datasheet(13/36 Pages) HOLTEK

13 / 36 page

Rev. 1.00

November 16, 2011

HT16L21

24×4 Display Mode

WhentheSP1bitissetto“1”andtheSP0bitissetto“1”,thedrivemodeisselectedas24segmentsby

4commonstogetherwith8LEDdrivingoutputs.

Output

COM3

COM2

COM1

COM0

Output

COM3

COM2

COM1

COM0 Address

SEG1

—

SEG0

—

00H

SEG3

—

SEG2

—

01H

SEG5

—

SEG4

—

02H

↓

SEG23

—

SEG22

—

0BH

—

Data

RAM mapping of 24×4 display mode

System Oscillator

ThetimingfortheinternallogicandtheLCDdrivesignalsaregeneratedbyaninternaloscillator.TheSystem

Clockfrequency(fSYS)determinestheLCDframefrequency.DuringinitialsystempowerontheSystemOscillator

willbeinthestopstate.

LCD Bias Generator

TheLCDsupplypowercancomefromtheexternalVLCDpinortheinternalregulatoroutputvoltagedetermined

usingtheInternalVoltageAdjustment(IVA)settingcommand.ThedeviceprovidesanexternalVLCDpinand

alsointegratesaninternalregulator.TheLCDvoltagemaybetemperaturecompensatedexternallythroughthe

VoltagesupplytotheVLCDpin.TheinternalregulatorcanalsoprovidetheLCDoperatingvoltage.Therefore,

thefull-scaleLCDvoltage(VOP)isobtainedfrom(VLCD–VSS)or(Vreg–VSS).

FractionalLCDbiasingvoltages,knownas1/2or1/3biasvoltage,areobtainedfromaninternalvoltagedividerof

fourseriesresistorsconnectedbetweenVLCDandVSS.Thecentreresistorcanbeswitchedoutofcircuitstoprovide

a1/2biasvoltagelevelconfiguration.

HT16L21 Datasheet(PDF) 13 Page - Holtek Semiconductor Inc

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