SIC403 datasheet(14/25 Pages) VISHAY

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Document Number: 66550

S11-1638-Rev. B, 15-Aug-11

Vishay Siliconix

SiC403

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

In the first method, the LDO is already in regulation and the

DC/DC converter is later enabled. As soon as the PGOOD

output goes high, the 32 cycles are started. The voltages at

the VLDO and VOUT pins are then compared; if the two

voltages are within ± 300 mV of each other, the VLDO pin

connects to the VOUT pin using an internal switch, and the

LDO is turned off.

In the second method, the DC/DC converter is already

running and the LDO is enabled. In this case the 32 cycles

are started as soon as the LDO reaches 90 % of its final

value. At this time, the VLDO and VOUT pins are compared,

and if within ± 300 mV the switch-over occurs and the LDO

is turned off.

Benefits of having a switchover circuit

The switchover function is designed to get maximum

efficiency out of the DC/DC converter. The efficiency for an

LDO is very low especially for high input voltages. Using the

switchover function we tie any rails connected to VLDO

through a switch directly to VOUT. Once switchover is

complete LDO is turned off which saves power. This gives us

the maximum efficiency out of the SiC403.

If the LDO output is used to bias the SiC403, then after

switchover the VOUT self biases the SiC403 and operates in

self-powered mode.

Steps to follow when using the on chip LDO to bias the

SiC403:

• Always tie the VDD to VLDO before enabling the LDO

• Enable the LDO before enabling the switcher

• LDO has a current limit of 40 mA at start-up, so do not

connect any load between VLDO and ground

• The current limit for the LDO goes up to 200 mA once the

VLDO reaches 90 % of its final values and can easily supply

the required bias current to the IC.

Switch-over Limitations on VOUT and VLDO

Because the internal switch-over circuit always compares

the VOUT and VLDO pins at start-up, there are limitations on

permissible combinations of VOUT and VLDO. Consider the

case where VOUT is programmed to 1.5 V and VLDO is

programmed to 1.8 V. After start-up, the device would

connect VOUT to VLDO and disable the LDO, since the two

voltages are within the ± 300 mV switch-over window.

To avoid unwanted switch-over, the minimum difference

between the voltages for VOUT and VLDO should be

± 500 mV.

It is not recommended to use the switch-over feature for an

output voltage less than 3 V since this does not provide

sufficient voltage for the gate-source drive to the internal

p-channel switch-over MOSFET.

Switch-Over MOSFET Parasitic Diodes

The switch-over MOSFET contains parasitic diodes that are

inherent to its construction, as shown in figure 10.

There are some important design rules that must be followed

to prevent forward bias of these diodes. The following two

conditions need to be satisfied in order for the parasitic

diodes to stay off.

• VDD  VLDO

• VDD  VOUT

If either VLDO or VOUT is higher than VDD, then the respective

diode will turn on and the SiC403 operating current will flow

through this diode. This has the potential of damaging the

device.

ENL Pin and VIN UVLO

The ENL pin also acts as the switcher under-voltage lockout

for the VIN supply. The VIN UVLO voltage is programmable

via a resistor divider at the VIN, ENL and AGND pins.

ENL is the enable/disable signal for the LDO. In order to

implement the VIN UVLO there is also a timing requirement

that needs to be satisfied.

If the ENL pin transitions low within 2 switching cycles and is

< 0.4 V, then the LDO will turn off but the switcher remains

on. If ENL goes below the VIN UVLO threshold and stays

above 1 V, then the switcher will turn off but the LDO remains

on.

The VIN UVLO function has a typical threshold of 2.6 V on the

VIN rising edge. The falling edge threshold is 2.4 V.

Note that it is possible to operate the switcher with the LDO

disabled, but the ENL pin must be below the logic low

threshold (0.4 V maximum).

ENL Logic Control of PWM Operation

When the ENL input is driven above 2.6 V, it is impossible to

determine if the LDO output is going to be used to power the

device or not. In self-powered operation where the LDO will

power the device, it is necessary during the LDO start-up to

hold the PWM switching off until the LDO has reached 90 %

of the final value. This is to prevent overloading the

current-limited LDO output during the LDO start-up.

However, if the switcher was previously operating (with EN/

PSV high but ENL at ground, and VDD supplied externally),

then it is undesirable to shut down the switcher.

To prevent this, when the ENL input is taken above 2.6 V

(above the VIN UVLO threshold), the internal logic checks the

PGOOD signal. If PGOOD is high, then the switcher is already

running and the LDO will run through the start-up cycle

without affecting the switcher. If PGOOD is low, then the LDO

Figure 10 - Switch-over MOSFET Parasitic Diodes

VOUT

VLDO

V5V

Parastic diode

Switchover

MOSFET

Switchover

control

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