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W29GL032CL7B Datasheet(PDF) 9 Page - Winbond |
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W29GL032CL7B Datasheet(HTML) 9 Page - Winbond |
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9 / 66 page  W29GL032C Publication Release Date: October 18, 2011 3 Preliminary - Revision E 4 BLOCK DIAGRAM CONTROL DECODER MAIN ARRAY OUTPUT BUFFER #CE #OE #WE RY/#BY #BYTE #RESET #WP/ACC DQ15/A-1 A0 A20 .. . .. .. .. .. .. .. .. .. .. . DQ15/A-1 DQ0 . . . . . . . . . . . . . . VCC EVIO VSS Figure 4-1 Block Diagram 5 PIN DESCRIPTION SYMBOL PIN NAME A0-A20 Address Inputs DQ0-DQ14 Data Inputs/Outputs DQ15/A-1 Word mode DQ15 is Data Input/Output Byte mode A-1 is Address Input #CE Chip Enable #OE Output Enable #WE Write Enable #WP/ACC Hardware Write Protect/ Acceleration Pin #BYTE Byte Enable #RESET Hardware Reset RY/#BY Ready/Busy Status VCC Power Supply EVIO Enhanced Variable IO Supply (No connect for top/bottom LFBGA64 configurations) VSS Ground NC No Connection Table 5-1 Pin Description |
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