9DB102BGLFT datasheet(9/13 Pages) IDT

9 / 13 page

IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2

852

REV K 04/01/10

ICS9DB102

Two Output Differential Buffer for PCIe Gen1 & Gen2

SMBus Table: Device Control Register, READ/WRITE ADDRESS (D4/D5)

Pin #

Name

Control Function Type

PWD

Bit 7

SW_EN

Enables SMBus

Control

Functions

controlled by

SMBus

registers

Functions

controlled by

device pins

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

PLL BW #adjust

Selects PLL

Bandwidth

Low BW

High BW

Bit 0

PLL Enable

Bypasses PLL for

board test

PLL bypassed

(fan out mode)

PLL enabled

(ZDB mode)

SMBus Table: Output Enable Register

Pin #

Name

Control Function Type

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMBus Table: Function Select Register

Pin #

Name

Control Function Type

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMBus Table: Vendor & Revision ID Register

Pin #

Name

Control Function Type

PWD

Bit 7

RID3

Bit 6

RID2

Bit 5

RID1

Bit 4

RID0

Bit 3

VID3

Bit 2

VID2

Bit 1

VID1

Bit 0

VID0

RESERVED

VENDOR ID

Byte 3

REVISION ID

Byte 2

RESERVED

Byte 1

RESERVED

Byte 0

RESERVED

9DB102BGLFT Datasheet(PDF) 9 Page - Integrated Device Technology

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