ICS9LPR501_09 datasheet(8/21 Pages) IDT

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IDTTM/ICSTM

64-pin CK505 w/Fully Integrated Voltage Regulator

1118M—11/24/09

Advance Information

ICS9LPR501

64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR

Datasheet

Electrical Characteristics - PCICLK/PCICLK_F

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS NOTES

Long Accuracy

ppm

see Tperiod min-max values

-100

100

ppm

1,2

33.33MHz output no spread

29.99700

30.00300

33.33MHz output spread

30.08421

30.23459

33.33MHz output no spread

29.49700

30.50300

33.33MHz output nominal/spread

29.56617

30.58421

Output High Voltage

VOH

IOH = -1 mA

2.4

Output Low Voltage

VOL

IOL = 1 mA

0.55

V OH @MIN = 1.0 V

-33

VOH@MAX = 3.135 V

-33

VOL @ MIN = 1.95 V

VOL @ MAX = 0.4 V

Rising Edge Slew Rate

tSLR

Measured from 0.8 to 2.0 V

V/ns

Falling Edge Slew Rate

tFLR

Measured from 2.0 to 0.8 V

V/ns

Pin to Pin Skew

tskew

VT = 1.5 V

250

Intential PCI to PCI delay

tskew

VT = 1.5 V

100

200

Duty Cycle

dt1

VT = 1.5 V

Jitter, Cycle to cycle

tjcyc-cyc

VT = 1.5 V

500

Tabs

Absolute min/max period

Output High Current

IOH

Output Low Current

IOL

Clock period

Tperiod

AC Electrical Characteristics - Low Power Differential Outputs

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS NOTES

Rising Edge Slew Rate

tSLR

Averaging on

2.5

V/ns

2, 3

Falling Edge Slew Rate

tFLR

Averaging on

2.5

V/ns

2, 3

Slew Rate Variation

tSLVAR

Averaging on

1, 10

Differential Voltage Swing

VSWING

Averaging off

300

Crossing Point Voltage

VXABS

Averaging off

300

550

1,4,5

Crossing Point Variation

VXABSVAR

Averaging off

140

1,4,9

Maximum Output VoltageVHIGH

Averaging off

1150

1,7

Minimum Output VoltageVLOW

Averaging off

-300

1,8

Duty Cycle

DCYC

Averaging on

CPU[1:0] Skew

CPUSKEW10

Differential Measurement

100

ps1

CPU[2_ITP:0] Skew

CPUSKEW20

Differential Measurement

150

ps1

SRC[10:0] Skew

SRCSKEW

Differential Measurement

3000

ps1,6

1Measurement taken for single ended waveform on a component test board (not in system)

2 Measurement taken from differential waveform on a component test board. (not in system)

3 Slew rate emastured through V_swing voltage range centered about differential zero

4 Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system)

9 The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to limit Vcross

induced modulation by setting C_cross_delta to be smaller than V_Cross absolute

5 Only applies to the differential rising edge (Clock rising, Clock# falling)

NOTES on DIF Output AC Specs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).

6 Total distributed intentional SRC to SRC skew. Maximum allowable interpair skew is 150 ps.

7 The max voltage including overshoot.

8 The min voltage including undershoot.

10 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising

meets Clock# falling. The median cross point is used to calculate the voltage

Clock Jitter Specs - Low Power Differential Outputs

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS NOTES

CPU Jitter - Cycle to Cycle

CPUJC2C

Differential Measurement

ps1

SRC Jitter - Cycle to Cycle

SRCJC2C

Differential Measurement

125

ps1

DOT Jitter - Cycle to Cycle

DOTJC2C

Differential Measurement

250

NOTES on DIF Output Jitter: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).

1Jitter specs are specified as measured on a clock characterization board. System designers need to take special care not to use these numbers, as the in-system performance

will be somewhat degraded. The receiver EMTS (chispet or CPU) will have the receiver

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