ICS9LPRS464 datasheet(6/23 Pages) IDT

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ICS9LPRS464

System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss

IDTTM/ICSTM

System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs

1377A—04/07/08

AC Electrical Characteristics - Low-Power DIF Outputs: CPUKG and HTT

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

Crossing Point Variation

∆V

CROSS

Single-ended Measurement

140

1,2,5

Frequency

Spread Specturm On

198.8

200

MHz

1,3

Long Term Accuracy

ppm

Spread Specturm Off

-300

+300

ppm

1,11

Rising Edge Slew Rate

SRISE

Differential Measurement

0.5

V/ns

1,4

Falling Edge Slew Rate

SFALL

Differential Measurement

0.5

V/ns

1,4

Slew Rate Variation

tSLVAR

Single-ended Measurement

CPU, DIF HTT Jitter - Cycle to

Cycle

CPUJC2C

Differential Measurement

150

1,6

Accumulated Jitter

tJACC

See Notes

1,7

Peak to Peak Differential Voltage

VD(PK-PK)

Differential Measurement

400

2400

1,8

Differential Voltage

Differential Measurement

200

1200

1,9

Duty Cycle

DCYC

Differential Measurement

Amplitude Variation

∆V

Change in VD DC cycle to cycle

-75

1,10

CPU Skew

CPUSKEW10

Differential Measurement

100

Guaranteed by design and characterization, not 100% tested in production.

Minimum Frequency is a result of 0.5% down spread spectrum

6 Max difference of t

CYCLE between any two adjacent cycles.

7 Accumulated tjc.over a 10 µs time period, measured with JIT2 TIE at 50ps interval.

8 VD(PK-PK) is the overall magnitude of the differential signal.

11 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz

VD(min) is the amplitude of the ring-back differential measurement, guaranteed by design, that ring-back will not cross 0V VD.

VD(max) is the largest amplitude allowed.

10 The difference in magnitude of two adjacent VD_DC measurements. VD_DC is the stable post overshoot and ring-back part of

the signal.

Single-ended measurement at crossing point. Value is maximum – minimum over all time. DC value of common mode is not

important due to the blocking cap.

Differential measurement through the range of ±100 mV, differential signal must remain monotonic and within slew rate spec when

crossing through this region.

5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK

and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#.

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