IXDN0036 datasheet(11/41 Pages) IXYS

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Ballast Demonstrator Operation

4-10

ATAVRFBKIT / EVLD001 User Guide

7597A–AVR–02/06

4.3

Startup and PFC

Description

Upon application of main power, the micontroller does not drive the PFC MOSFET Q3.

The C9 capacitor is charged to the peak line voltage.

The depletion FET Q1 and the Zener Diode provide a DC voltage (UVLO) with enough

current to supply the control part of the ballast.

As soon as the microcontroller request the ballast to start, the PFC is started according

to the following sequence.

Microcontroller checks that the DC bus voltage is 0.9 times the haversine peak

and the under voltage lockout (UVLO) requirements are met, a series of fixed

width soft-start pulses are sent to the PFC MOSFET (Q3) at 10 µS at a 20 KHz

rate. At very low load currents the bus voltage should rise to 380V. If the bus

rises to 410 VDC all PFC pulses stop. As the 380V drops, the zero crossing

detector PD7 starts to sense a zero crossing from the PFC transformer second-

ary. A 380V DC bus and a zero crossing event starts the PFC control loop.

Checks are made for the presence of the rectified power (haversine) and bus voltage

throughout normal operation. Mains sense at PB7 < 0.848 (90 VAC) or > 2.497 (265

VAC) peak faults the PFC to off, turns off the PFC MOSFET (Q3) and initiates a restart.

The control consists of measuring the error between VBUS and 380V (2.27V at PB2) to

determine the PFC drive pulse width (PW). The PW is proportional to the error, and has

to be constant over a complete half period. The update is done each time the haversine

reaches zero.

The maximum curent the PFC MOSFET (Q3) can sustain is 4.5A. The relation between

PW and and the peak current in PFC MOSFET (Q3) is:

PW = t = L x Ipk / Vhaversine_max

With L at 700µH and Ipk at 4.5A, PWmax = 8.5µS at high line (265 Vrms).

With L at 700µH and Ipk at 4.5A, PWmax = 24.7µS at high line (90 Vrms).

This also effectively limits the FET dissipation under upset conditions. Under

normal operation, a pulse width maximum of 25µS is allowed for a maximum

bus voltage error with the high line limitation. Regulation of 1% of the VBUS is

achieved with this control scheme.

After the PFC FET ON pulse, the PFC inductor flyback boosts the voltage through the

PFC diode to the bulk filter capacitor. The boost current decays as measured by the

inductor secondary. After the current goes to zero, the next pulse is started. This

ensures operation in a critical conduction boost mode. The current zero crossing detec-

tion of PD7 sets the PFC off time. This off time is effectively proportional to the

haversine amplitude with the lowest PFC frequency occurring at the haversine crest and

the highest frequency at the haversine zero. Because of the haversine voltage and

di=v*dt/L, the mains current envelope should follow the voltage for near unity power fac-

tor. This assumes a nearly constant error (di) of the 380 VDC bus over each haversine

period.

IXDN0036 Datasheet(PDF) 11 Page - IXYS Corporation

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