MAX1302_12 datasheet(21/31 Pages) MAXIM

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Start Bit

Communication with the MAX1302 is accomplished

using the three input data word formats shown in

Table 3. Each input data word begins with a start bit.

The start bit is defined as the first high bit clocked into

DIN with CS low when any of the following are true:

• Data conversion is not in process and all data from

the previous conversion has clocked out of DOUT.

• The device is configured for operation in external

clock mode (mode 0) and previous conversion-result

bits B15–B3 have clocked out of DOUT.

• The device is configured for operation in external

acquisition mode (mode 1) and previous conversion-

result bits B15–B7 have clocked out of DOUT.

• The device is configured for operation in internal

clock mode, (mode 2) and previous conversion-

result bits B15–B4 have clocked out of DOUT.

Output Data Format

Output data is clocked out of DOUT in offset binary for-

mat on the falling edge of SCLK, MSB first (B15). For

output binary codes, see the

Transfer Function section

and Figures 12, 13, and 14.

Configuring Analog Inputs

Each analog input has two configurable parameters:

• Single-ended or true-differential input

• Input voltage range

These parameters are configured using the analog input

configuration byte as shown in Table 2. Each analog

input has a dedicated register to store its input configura-

tion information. The timing diagram of Figure 15 shows

how to write to the analog input configuration registers.

Figure 16 shows DOUT and SSTRB timing.

Transfer Function

An ADC’s transfer function defines the relationship

between the analog input voltage and the digital output

code. Figures 12, 13, and 14 show the MAX1302 transfer

functions. The transfer function is determined by the fol-

lowing characteristics:

• Analog input voltage range

• Single-ended or differential configuration

• Reference voltage

The axes of an ADC transfer function are typically in least

significant bits (LSBs). For the MAX1302, an LSB is calcu-

lated using the following equation:

where N is the number of bits (N = 16) and FSR is the

full-scale range (see Figures 7 and 8).

4 096

LSB

FSR

REF

8-Channel, ±VREF Multirange Inputs,

Serial 16-Bit ADC

______________________________________________________________________________________

INPUT VOLTAGE (V)

-2

-4

-6

-4

-2

-6

-8

VREF = 4.096V

Figure 9. Common-Mode Voltage vs. Input Voltage (FSR = VREF)

INPUT VOLTAGE (V)

-2

-4

-6

-4

-2

-6

-8

VREF = 4.096V

Figure 10. Common-Mode Voltage vs. Input Voltage (FSR = 2 x

VREF)

INPUT VOLTAGE (V)

-2

-4

-6

-4

-2

-6

-8

VREF = 4.096V

Figure 11. Common-Mode Voltage vs. Input Voltage (FSR = 4 x

VREF)

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