The pins described in Table VIII comprise the physical interface between the user’s programming device and the

serial port of the AD9254. The SCLK and CSB pins function as inputs when using the SPI interface. The SDIO pin is

bidirectional, functioning as an input during write phases and as an output during readback.

The SPI interface is flexible enough to be controlled by either PROM or PIC microcontrollers. This provides the user

with the ability to use an alternate method to program the ADC. One method is described in detail in Application Note

AN-812, Microcontroller-Based Serial Port Interface Boot Circuit.

When the SPI interface is not used, some pins serve a dual function. When strapped to AVDD or ground during device

power on, the pins are associated with a specific function.

n applications that do not interface to the SPI control registers, the SDIO/DCS and SCLK/DFS pins serve as stand-

alone CMOS-compatible control pins. When the device is powered up, it is assumed that the user intends to use the

pins as static control lines for the output data format and duty cycle stabilizer (see Table V). In this mode, the CSB

chip select should be connected to AVDD, which disables the serial port interface. For more information, see the

Interfacing to High Speed ADCs via SPI user manual.

Each row in the memory map register table has eight address locations. The memory map is roughly divided into

three sections: the chip configuration registers map (Address 0x00 to Address 0x02), the device index and transfer

registers map (Address 0xFF), and the ADC functions map (Address 0x08 to Address 0x18).

Table X displays the register address number in hexadecimal in the first column. The last column displays the default

value for each hexadecimal address. The Bit 7 (MSB) column is the start of the default hexadecimal value given. For

example, Hexadecimal Address 0x14, output_phase, has a hexadecimal default value of 0x00. This means Bit 3 = 0,

Bit 2 = 0, Bit 1 = 1, and Bit 0 = 1 or 0011 in binary. This setting is the default output clock or DCO phase adjust option.

The default value adjusts the DCO phase 90° relative to the nominal DCO edge and 180° relative to the data edge.

For more information on this function, consult the Interfacing to High Speed ADCs via SPI user manual.

Locations marked as open are currently not supported for this device. When required, these locations should be

written with 0s. Writing to these locations is required only when part of an address location is open (for example,

Address 0x14). If the entire address location is open (Address 0x13), then the address location does not need to be

written.

Coming out of reset, critical registers are loaded with default values. The default values for the registers are shown in

Table X.

An explanation of two registers follows:

• “Bit is set” is synonymous with “Bit is set to Logic 1” or “Writing Logic 1 for the bit.”