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LTM9012 Datasheet(PDF) 12 Page - Linear Technology |
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LTM9012 Datasheet(HTML) 12 Page - Linear Technology |
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12 / 28 page  LTM9012 12 9012f pin FuncTions PAR/SER (P10): Programming Mode Selection Pin. Con- necttogroundtoenabletheserialprogrammingmode.CS, SCK, SDI and SDO become a serial interface that controls the A/D operating modes. Connect to VDD to enable the parallel programming mode where CS, SCK, SDI and SDO become parallel logic inputs that control a reduced set of the A/D operating modes. PAR/SER should be connected directly to ground or the VDD of the part and not be driven by a logic signal. VREF (P11): Reference Voltage Output. VREF is internally bypassed to ground with a 2.2μF ceramic capacitor, nomi- nally 1.25V. SENSE (N11): Reference Programming Pin. Connecting SENSE to VDD selects the internal reference and a ±0.1V input range. Connecting SENSE to ground selects the internal reference and a ±0.05V input range. An external reference between 0.625V and 1.3V applied to SENSE selects an input range of ±0.08 • VSENSE. SENSE is inter- nally bypassed to ground with a 0.1μF ceramic capacitor. LVDS Outputs All pins in this section are differential LVDS outputs. The output current level is programmable. There is an optional internal 100Ω termination resistor between the pins of each LVDS output pair. OUT1A–/OUT1A+, OUT1B–/OUT1B+ (Q9/Q10, R11/R12): Serial data outputs for Channel 1. In 1-lane output mode only OUT1A–/OUT1A+ are used. OUT2A–/OUT2A+, OUT2B–/OUT2B+ (R9/R10, S11/S12): Serial data outputs for Channel 2. In 1-lane output mode only OUT2A–/OUT2A+ are used. OUT3A–/OUT3A+, OUT3B–/OUT3B+ (S2/S3, R4/R5): Se- rial data outputs for Channel 3. In 1-lane output mode only OUT3A–/OUT3A+ are used. OUT4A–/OUT4A+, OUT4B–/OUT4B+ (R2/R3, Q4/Q5): Se- rial data outputs for Channel 4. In 1-lane output mode only OUT4A–/OUT4A+ are used. FR–/FR+ (S4/S5): Frame Start Output. DCO–/DCO+ (S9/S10): Data Clock Output. 1 2 3 4 5 6 7 8 9 10 11 12 13 A GND CH4+ CH4– GND CH3+ CH3– GND CH2+ CH2– GND CH1+ CH1– GND B GND GND GND GND GND GND GND GND GND GND GND GND GND C GND VCC3 GND GND GND VCC3 GND VCC2 GND GND GND VCC2 GND D GND GND SHDN3 GND GND GND GND GND SHDN2 GND GND GND GND E GND GND GND GND GND GND GND GND GND GND GND GND GND F GND GND GND GND GND GND GND GND GND GND GND GND GND G SHDN4 GND GND GND GND GND GND GND GND GND SHDN1 GND GND H VCC4 GND GND VCC4 GND GND GND GND GND VCC1 GND GND VCC1 J GND GND GND GND GND GND GND GND GND GND GND GND GND K GND GND GND GND GND GND GND GND GND GND GND GND GND L GND GND GND GND GND GND GND GND GND GND GND GND GND M GND GND GND GND GND GND GND GND GND GND GND GND GND N ENC+ GND GND VDD VDD GND GND GND VDD VDD SENSE GND GND P ENC– GND SDI CS SCK GND GND GND SDO PAR/SER REF GND GND Q GND GND GND D4B– D4B+ GND GND GND D1A– D1A+ GND GND GND R GND D4A– D4A+ D3B– D3B+ GND OVDD OVDD D2A– D2A+ D1B– D1B+ GND S GND D3A– D3A+ FR– FR+ GND GND OVDD DCO– DCO+ D2B– D2B+ GND pin conFiguraTion Table |
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