Sensors

Freescale Semiconductor, Inc.

15

MMA685x

3.1.6.5

ARM Configuration Bits (A_CFG[2:0])

The ARM Configuration Bits (A_CFG[2:0]) select the mode of operation for the ARM/PCM pins.

3.1.7

Axis Configuration Register (DEVCFG_X)

The Axis configuration register is a read/write register which contains axis specific configuration information. This register can

be written during initialization, but is locked once the ENDINIT bit is set. This register is included in the writable register CRC

check. Refer to Section 3.2.2 for details

3.1.7.1

Self-Test Control (ST)

The ST bit enables and disables the self-test circuitry. Self-test circuitry is enabled if a logic ‘1’ is written to ST and the ENDINIT

bit has not been set. Enabling the self-test circuitry results in a positive acceleration value. Self-test deflection values are specified

in Section 2.4. ST is always cleared following internal reset.

When the self-test circuitry is active, the offset cancellation block and the offset monitor status are suspended, and the status

bits in the Acceleration Data Request Response will indicate “Self-Test Active”. Reference Section 3.8.4 and Section 4.2 for de-

ified in Section 2.4 expires. However, the status bits in the Acceleration Data Request Response will immediately indicate that

self-test has been deactivated.

3.1.7.2

Reserved Bits (Reserved)

Bits 6 through 4 of the DEVCFG_X register are reserved. A write to the reserved bits must always be logic ‘0’ for normal device

operation and performance.

Table 9. Arming Output Configuration

A_CFG[2]

A_CFG[1]

A-CFG[0]

Operating Mode

Output Type

Reference

0

0

0

Arm Output Disabled

Hi Impedance

0

0

1

PCM Output

Digital Output

Section 3.8.10

0

1

0

Moving Average Mode

Active High with Pulldown Current

Section 3.8.9.1

0

1

1

Moving Average Mode

Active Low with Pullup Current

Section 3.8.9.1

1

0

0

Count Mode

Active High with Pulldown Current

Section 3.8.9.2

1

0

1

Count Mode

Active Low with Pullup Current

Section 3.8.9.2

1

1

0

Unfiltered Mode

Active High with Pulldown Current

Section 3.8.9.3

1

1

1

Unfiltered Mode

Active Low with Pullup Current

Section 3.8.9.3

Table 10. Axis Configuration Registers

Location

Bit

Address

Register

76543210

$0C

DEVCFG_X

ST

Reserved

Reserved

Reserved

LPF[3]

LPF[2]

LPF[1]

LPF[0]

Reset Value

0

0000000