MPC8569E datasheet(50/127 Pages) FREESCALE

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MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

DDR2 and DDR3 SDRAM Controller

Freescale Semiconductor

2.4.2.2

DDR2 and DDR3 SDRAM Interface Output AC Timing Specifications

The following table contains the output AC timing targets for the DDR2 and DDR3 SDRAM interface.

Table 20. DDR2 and DDR3 SDRAM Interface Output AC Timing Specifications6

At recommended operating conditions with GVDD of 1.8 V ± 5% for DDR2 or 1.5 V ± 5% for DDR3.

Parameter

Symbol1

Min

Max

Unit

Notes

MCK[n] cycle time

tMCK

2.5

ADDR/CMD output setup with respect to

MCK

tDDKHAS

800 MHz

667 MHz

533 MHz

400 MHz

0.9177

0.888

1.10

1.48

1.95

—

ADDR/CMD output hold with respect to

MCK

tDDKHAX

800 MHz

667 MHz

533 MHz

400 MHz

0.9177

0.888

1.10

1.48

1.95

—

MCS[n] output setup with respect to MCK

tDDKHCS

800 MHz

667 MHz

533 MHz

400 MHz

0.917

1.10

1.48

1.95

—

MCS[n] output hold with respect to MCK

tDDKHCX

800 MHz

667 MHz

533 MHz

400 MHz

0.917

1.10

1.48

1.95

—

MCK to MDQS skew

tDDKHMH

800 MHz

≤ 667 MHz

–0.375

–0.6

0.375

0.6

MPC8569E Datasheet(PDF) 50 Page - Freescale Semiconductor, Inc

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