MMA8451Q datasheet(8/52 Pages) FREESCALE

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MMA8451Q

Sensors

Freescale Semiconductor, Inc.

2.3

I2C Interface Characteristic

Figure 5. I2C Slave Timing Diagram

Table 4. I2C Slave Timing Values(1)

1. All values referred to VIH (min) and VIL (max) levels.

Parameter

Symbol

I2C Fast Mode

Unit

Min

Max

SCL Clock Frequency

Pullup = 4.7 k

Ω, Cb = 20 pF

Pullup = 4.7 k

Ω, Cb = 40 pF

Pullup = 4.7 k

Ω, Cb = 400 pF

Pullup = 1 k

Ω, Cb = 20 pF

Pullup = 1 k

Ω, Cb = 400 pF

fSCL

2.250

100

Nonfunctional

4.50

750

MHz

kHz

—

MHz

kHz

Bus Free Time between STOP and START Condition

tBUF

1.3

μs

Repeated START Hold Time

tHD;STA

0.6

μs

Repeated START Setup Time

tSU;STA

0.6

μs

STOP Condition Setup Time

tSU;STO

0.6

μs

SDA Data Hold Time(2)

2. tHD;DAT is the data hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge.

tHD;DAT

0.5

0.9(3)

3. The maximum tHD;DAT could be 3.45 μs and 0.9 μs for Standard mode and Fast mode, but must be less than the maximum of tVD;DAT or tVD;ACK

by a transition time.

μs

SDA Valid Time (4)

4. tVD;DAT = time for Data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).

tVD;DAT

0.9(3)

μs

SDA Valid Acknowledge Time (5)

5. tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).

tVD;ACK

0.9(3)

μs

SDA Setup Time

tSU;DAT

100(6)

6. A Fast mode I2C device can be used in a Standard mode I2C system, but the requirement tSU;DAT 250 ns must then be met. This will

automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the

SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard mode I

specification) before the SCL line is released. Also the acknowledge timing must meet this setup time

SCL Clock Low Time

tLOW

4.7

μs

SCL Clock High Time

tHIGH

μs

SDA and SCL Rise Time

1000

SDA and SCL Fall Time (7) (8)

7. Cb = total capacitance of one bus line in pF.

8. The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns.

This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding

the maximum specified tf.

300

Pulse width of spikes on SDA and SCL that must be suppressed by input filter

tSP

handbook, full pagewidth

MSC610

tSU;STO

tSU;STA

tHD;STA

tHIGH

tLOW

tSU;DAT

tHD;DAT

SDA

SCL

tBUF

tSP

tHD;STA

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