CY29973

Document Number: 38-07291 Rev. *E

Page 7 of 10

Dynamic Supply Current

QA and QB at 60 MHz,

QC at 120 MHz, CL=30 pF

–225

–

mA

QA and QB at 25 MHz,

QC at 50 MHz, CL=30 pF

–125

–

Input Pin Capacitance

–

4

–

pF

Output Impedance

15

18

22



AC Electrical Specifications

Parameter

Description

Conditions

Min

Typ.

Max

Unit

Tr/Tf

TCLK Input Rise or Fall

–

3.0

ns

Fref

Reference Input Frequency

Note 8

–

Note 8

MHz

FrefDC

Reference Input Duty Cycle

25

–

75

%

Fvco

PLL VCO Lock Range

200

–

480

MHz

Tlock

Maximum PLL lock Time

–

–

10

ms

Tr/Tf

Output Clocks Rise or Fall Time[9]

0.8 V to 2.0 V

0.15

–

1.2

ns

Fout

Maximum Output Frequency

Q (

2)

–

–

125

MHz

Q (

4)

–

–

120

Q (

6)

–

–

80

Q (

8)

–

–

60

FoutDC

Output Duty Cycle[9]

TCYCLE/2 – 750

–

TCYCLE/2 + 750

ps

tpZL, tpZH Output Enable Time[9](all outputs)

2–

10

ns

tpLZ, tpHZ Output Disable Time[9](all outputs)

2–

8

ns

TCCJ

Cycle to Cycle Jitter[9](peak to peak)

–±100

–

ps

TSKEW

Any Output to Any Output Skew[9, 10]

–250

350

ps

–225

–25

175

ps

Tpd

TCLK0

QFB =(³8)

–70

130

330

TCLK1

–130

70

270

DC Electrical Specifications

Parameter

Description

Conditions

Min

Typ

Max

Unit

Notes

7. Parameters are guaranteed by design and characterization. Not 100% tested in production.

8. Maximum and minimum input reference is limited by VC0 lock range.

9. Outputs loaded with 30pF each.

10. 50

 transmission line terminated into VDD/2.

11. Tpd is specified for a 50MHz input reference. Tpd does not include jitter.

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