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Digital Inputs

Internal

DigitalIn

110-

Ω

Termination

Resistor

Internal

Digital In

D[13:0]A

D[13..0]A

D[13..0]B

D[13:0]B

DGND

DV

DD

DAC5675-EP

DAC5675-EP

Internal

Digital In

DGND

Digital Input

DAC5675-EP

Clock Input

DAC5675-EP

SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006

APPLICATION INFORMATION (continued)

The DAC5675 uses a low-voltage differential signaling (LVDS) bus input interface. The LVDS features a low

differential voltage swing with low constant power consumption (4 mA per complementary data input) across

frequency. The differential characteristic of LVDS allows for high-speed data transmission with low

electromagnetic interference (EMI) levels. The LVDS input minimum and maximum input threshold table lists the

LVDS input levels. Figure 14 shows the equivalent complementary digital input interface for the DAC5675, valid

for pins D[13:0]A and D[13:0]B. Note that the LVDS interface features internal 110-

Ω resistors for proper

termination. Figure 2 shows the LVDS input timing measurement circuit and waveforms. A common-mode level

Figure 15 shows a schematic of the equivalent CMOS/TTL-compatible digital inputs of the DAC5675, valid for

the SLEEP pin.

Figure 14. LVDS Digital Equivalent Input

Figure 15. CMOS/TTL Digital Equivalent Input

The DAC5675 features differential LVPECL-compatible clock inputs (CLK, CLKC). Figure 16 shows the

equivalent schematic of the clock input buffer. The internal biasing resistors set the input common-mode voltage

to approximately 2 V, while the input resistance is typically 670

Ω. A variety of clock sources can be ac-coupled

to the device, including a sine-wave source (see Figure 17).

14

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