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K12P80M50SF4 Datasheet(PDF) 21 Page - Freescale Semiconductor, Inc |
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K12P80M50SF4 Datasheet(HTML) 21 Page - Freescale Semiconductor, Inc |
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21 / 58 page ![]() 2. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air) with the single layer board horizontal. For the LQFP, the board meets the JESD51-3 specification. For the MAPBGA, the board meets the JESD51-9 specification. 3. Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental Conditions—Forced Convection (Moving Air) with the board horizontal. 4. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions—Junction-to-Board. Board temperature is measured on the top surface of the board near the package. 5. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 6. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air). 6 Peripheral operating requirements and behaviors 6.1 Core modules 6.1.1 JTAG electricals Table 12. JTAG limited voltage range electricals Symbol Description Min. Max. Unit Operating voltage 2.7 3.6 V J1 TCLK frequency of operation • Boundary Scan • JTAG and CJTAG • Serial Wire Debug 0 0 0 10 25 50 MHz J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width • Boundary Scan • JTAG and CJTAG • Serial Wire Debug 50 20 10 — — — ns ns ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 0 — ns J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1 — ns J11 TCLK low to TDO data valid — 17 ns J12 TCLK low to TDO high-Z — 17 ns J13 TRST assert time 100 — ns J14 TRST setup time (negation) to TCLK high 8 — ns Peripheral operating requirements and behaviors K12 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. Freescale Semiconductor, Inc. 21 |
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