ThunderLAN

™ TNETE100A

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN

SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996

23

POST OFFICE BOX 1443

MIN

TYP

MAX

UNIT

td(VDDH–FXTL1V)

Delay time from minimum VDD high level to first valid FXTL1 full swing period

100‡

ms

tw(H)

Pulse duration at FXTL1 high

13‡

ns

tw(L)

Pulse duration at FXTL1 low

13‡

ns

tt

Transition time of FXTL1

7

ns

tc

Cycle time, FXTL1

50

ns

Tolerance of FXTL1 input frequency

"0.01

%

† The FXTL signal can be driven by either a 20-MHz crystal using the FXTL1 and FXTL2 pins or by a 20-MHz crystal oscillator driving the FXTL1

pin.

‡ This specification is provided as an aid to board design. This specification is not tested during manufacturing testing.

FXTL1

VDD

td(VDDH–FXTL1V)

Minimum VDD High Level

tc

tw(H)

tw(L)

tt

tt

Figure 10. Crystal Oscillator Timing