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KL14 Datasheet(PDF) 13 Page - Freescale Semiconductor, Inc |
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KL14 Datasheet(HTML) 13 Page - Freescale Semiconductor, Inc |
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13 / 20 page ![]() • Up to 32 interrupt sources • Includes a single non-maskable interrupt 4.5.1.3 Wake-up Interrupt Controller (WIC) • Supports interrupt handling when system clocking is disabled in low power modes • Takes over and emulates the NVIC behavior when correctly primed by the NVIC on entry to very-deep-sleep • A rudimentary interrupt masking system with no prioritization logic signals for wake-up as soon as a non-masked interrupt is detected • Contains no programmer’s model visible state and is therefore invisible to end users of the device other than through the benefits of reduced power consumption while sleeping 4.5.1.4 Debug Controller • 2-pin serial wire debug (SWD) provides external debugger interface • Micro trace buffer (MTB) provides simple execution trace capability and operates as a simple AHB-Lite SRAM controller System Modules 4.5.2.1 Power Management Control Unit (PMC) • Separate digital (regulated) and analog (referenced to digital) supply outputs • Programmable power saving modes • No output supply decoupling capacitors required • Available wake-up from power saving modes via RTC and external inputs • Integrated Power-on Reset (POR) • Integrated Low Voltage Detect (LVD) with reset (brownout) capability • Selectable LVD trip points • Programmable Low Voltage Warning (LVW) interrupt capability • Buffered bandgap reference voltage output • Factory programmed trim for bandgap and LVD • 1 kHz Low Power Oscillator (LPO) 4.5.2.2 DMA Channel Multiplexer (DMA MUX) • 4 independently selectable DMA channel routers • 2 periodic trigger sources available • Each channel router can be assigned to 1 of 63 possible peripheral DMA sources 4.5.2.3 DMA Controller Four independently programmable DMA controller channels provides the means to directly transfer data between system memory and I/O peripherals • DMA controller is capable of functioning in run, wait and stop modes of operation • Dual-address transfers via 32-bit master connection to the system bus • Data transfers in 8-, 16-, or 32-bit blocks • Continuous-mode or cycle-steal transfers from software or peripheral initiation 4.5.2 System Modules KL14/KL15 Product Brief, Rev. 2, 6/2012 Freescale Semiconductor, Inc. Preliminary 13 General Business Information |
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