SC9301 datasheet(24/29 Pages) SEMTECH

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SC9301

Applications Information (continued)

The output inductor value may change with current. This

will change the output ripple and therefore will have a

minor effect on the DC output voltage. The output ESR

also affects the output ripple and thus has a minor effect

on the DC output voltage.

Switching Frequency Variations

The switching frequency will vary depending on line and

load conditions. The line variations are a result of fixed

propagation delays in the on-time one-shot, as well as

unavoidable delays in the external MOSFET switching. As

increases, these factors make the actual DH on-time

slightly longer than the ideal on-time. The net effect is

that frequency tends to falls slightly with increasing input

voltage.

The switching frequency also varies with load current as a

result of the power losses in the MOSFETs and the induc-

tor. For a conventional PWM constant-frequency con-

verter, as load increases the duty cycle also increases

slightly to compensate for IR and switching losses in the

MOSFETs and inductor. A adaptive on-time converter

must also compensate for the same losses by increasing

the effective duty cycle (more time is spent drawing

energy from V

as losses increase). Because the on-time is

essentially constant for a given V

OUT

combination, to

offset the losses the off-time will reduce slightly as load

increases. The net effect is that switching frequency

increases slightly with increasing load.

PCB Layout Guidelines

The optimum layout for the SC9301 is shown in Figure 16.

This layout shows an integrated FET buck regulator with a

maximum current of 10A. The total PCB area is approxi-

mately 25 x 29 mm with single side components.

Critical Layout Guidelines

The following critical layout guidelines must be followed

to ensure proper performance of the device.

IC Decoupling capacitors

PGND plane

AGND island

FB, VOUT, and other analog control signals

BST, ILIM, and LX

and C

OUT

placement and Current Loops

IC Decoupling Capacitors

A 1 μF capacitor must be located as close as pos-

sible to the IC and directly connected to pins 3

(VDD) and 4 (AGND).

Another 1 μF capacitor must be located as close

as possible to the IC and directly connected to

pins 3 (VDD) and PGND plane.

PGND Plane

PGND requires its own copper plane with no

other signal traces routed on it.

Copper planes, multiple vias and wide traces are

needed to connect PGND to input capacitors,

output capacitors, and the PGND pins on the IC.

The PGND copper area between the input

capacitors, output capacitors and PGND pins

must be as tight and compact as possible to

reduce the area of the PCB that is exposed to

noise due to current flow on this node.

AGND Island

AGND should have its own island of copper with

no other signal traces routed on this layer that

connects the AGND pins and pad of the IC to the

analog control components.

All of the components for the analog control cir-

cuitry should be located so that the connections

to AGND are done by wide copper traces or vias

down to AGND.

•

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