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PIC16F1512 Datasheet(PDF) 21 Page - Microchip Technology |
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PIC16F1512 Datasheet(HTML) 21 Page - Microchip Technology |
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21 / 348 page  TABLE 3-3: PIC16(L)F1512 MEMORY MAP (BANKS 0-7) Legend: = Unimplemented data memory locations, read as ‘0’. Note 1: PIC16F1512 only. BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 000h Core Registers (Table 3-2) 080h Core Registers (Table 3-2) 100h Core Registers (Table 3-2) 180h Core Registers (Table 3-2) 200h Core Registers (Table 3-2) 280h Core Registers (Table 3-2) 300h Core Registers (Table 3-2) 380h Core Registers (Table 3-2) 00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh 00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch — 28Ch — 30Ch — 38Ch — 00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh — 30Dh — 38Dh — 00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh —28Eh —30Eh —38Eh — 00Fh —08Fh —10Fh —18Fh —20Fh —28Fh —30Fh —38Fh — 010h PORTE 090h TRISE 110h —190h — 210h WPUE 290h — 310h — 390h — 011h PIR1 091h PIE1 111h — 191h PMADRL 211h SSP1BUF 291h CCPR1L 311h — 391h — 012h PIR2 092h PIE2 112h — 192h PMADRH 212h SSP1ADD 292h CCPR1H 312h — 392h — 013h —093h —113h — 193h PMDATL 213h SSP1MSK 293h CCP1CON 313h — 393h — 014h —094h —114h — 194h PMDATH 214h SSP1STAT 294h — 314h — 394h IOCBP 015h TMR0 095h OPTION_REG 115h — 195h PMCON1 215h SSP1CON1 295h — 315h — 395h IOCBN 016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSP1CON2 296h — 316h — 396h IOCBF 017h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON(1) 217h SSP1CON3 297h — 317h — 397h — 018h T1CON 098h —118h —198h —218h — 298h CCPR2L 318h — 398h — 019h T1GCON 099h OSCCON 119h — 199h RCREG 219h — 299h CCPR2H 319h — 399h — 01Ah TMR2 09Ah OSCSTAT 11Ah — 19Ah TXREG 21Ah — 29Ah CCP2CON 31Ah —39Ah — 01Bh PR2 09Bh ADRES0L 11Bh — 19Bh SPBRGL 21Bh —29Bh —31Bh —39Bh — 01Ch T2CON 09Ch ADRES0H 11Ch — 19Ch SPBRGH 21Ch — 29Ch — 31Ch — 39Ch — 01Dh — 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh — 29Dh — 31Dh — 39Dh — 01Eh — 09Eh ADCON1 11Eh — 19Eh TXSTA 21Eh —29Eh —31Eh —39Eh — 01Fh —09Fh —11Fh — 19Fh BAUDCON 21Fh —29Fh —31Fh —39Fh — 020h General Purpose Register 80 Bytes 0A0h General Purpose Register 32 Bytes 120h Unimplemented Read as ‘0’ 1A0h Unimplemented Read as ‘0’ 220h Unimplemented Read as ‘0’ 2A0h Unimplemented Read as ‘0’ 320h Unimplemented Read as ‘0’ 3A0h Unimplemented Read as ‘0’ 0BFh 0C0h Unimplemented Read as ‘0’ 06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh 070h Common RAM 0F0h Common RAM (Accesses 70h – 7Fh) 170h Common RAM (Accesses 70h – 7Fh) 1F0h Common RAM (Accesses 70h – 7Fh) 270h Common RAM (Accesses 70h – 7Fh) 2F0h Common RAM (Accesses 70h – 7Fh) 370h Common RAM (Accesses 70h – 7Fh) 3F0h Common RAM (Accesses 70h – 7Fh) 07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh |
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