Integrated Silicon Solution, Inc. — www.issi.com

1

Rev. A

05/14/2012

Copyright©2012IntegratedSiliconSolution,Inc.Allrightsreserved.ISSIreservestherighttomakechangestothisspecificationanditsproductsatanytimewithout

notice.ISSIassumesnoliabilityarisingoutoftheapplicationoruseofanyinformation,productsorservicesdescribedherein.Customersareadvisedtoobtainthelat-

estversionofthisdevicespecificationbeforerelyingonanypublishedinformationandbeforeplacingordersforproducts.

IntegratedSiliconSolution,Inc.doesnotrecommendtheuseofanyofitsproductsinlifesupportapplicationswherethefailureormalfunctionoftheproductcanreason-

ablybeexpectedtocausefailureofthelifesupportsystemortosignificantlyaffectitssafetyoreffectiveness.Productsarenotauthorizedforuseinsuchapplications

unlessIntegratedSiliconSolution,Inc.receiveswrittenassurancetoitssatisfaction,that:

a.)theriskofinjuryordamagehasbeenminimized;

b.)theuserassumeallsuchrisks;and

c.)potentialliabilityofIntegratedSiliconSolution,Incisadequatelyprotectedunderthecircumstances

IS61WV3216DALL/DALS

IS61WV3216DBLL/DBLS

IS64WV3216DBLL/DBLS

FEATURES

HIGHSPEED:(IS61/64WV3216DALL/DBLL)

• High-speedaccesstime:8,10,12,20ns

• LowActivePower:135mW(typical)

• LowStandbyPower:12µW(typical)

CMOSstandby

LOWPOWER:(IS61/64WV3216DALS/DBLS)

• High-speedaccesstime:25,35ns

• LowActivePower:55mW(typical)

• LowStandbyPower:12µW(typical)

CMOSstandby

• Singlepowersupply

• Fullystaticoperation:noclockorrefresh

required

• Threestateoutputs

• Datacontrolforupperandlowerbytes

• IndustrialandAutomotivetemperaturesupport

• Lead-freeavailable

32K x 16 HIGH SPEED ASYNCHRONOUS

CMOS STATIC RAM

DESCRIPTION

The

are high-speed, 524,288-bit static RAMs organized as

32,768wordsby16bits.Itisfabricatedusing

performanceCMOStechnology.Thishighlyreliableprocess

coupledwithinnovativecircuitdesigntechniques,yields

high-performanceandlowpowerconsumptiondevices.

When CE is HIGH (deselected), the device assumes a

standbymodeatwhichthepowerdissipationcanbere-

duceddownwithCMOSinputlevels.

EasymemoryexpansionisprovidedbyusingChipEnable

andOutputEnableinputs,CEandOE.TheactiveLOW

WriteEnable(WE)controlsbothwritingandreadingofthe

memory.AdatabyteallowsUpperByte(UB)andLower

Byte(LB)access.

TheIS61WV3216DAxx/DBxxandIS64WV3216DBxxare

packagedintheJEDECstandard44-pinTSOPTypeIIand

48-pinMiniBGA(6mmx8mm).

FUNCTIONAL BLOCK DIAGRAM

MAY 2012

A0-A14

CE

OE

WE

32K x 16

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

I/O

DATA

CIRCUIT

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

UB

LB