TMP87PM48DFG datasheet(3/38 Pages) TOSHIBA

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Datasheet Modifications: I2C Bus Mode Control

The following problem is included in the explanation of the I2C bus function of this data sheet.

It will guide the correction as follows. Please read it for the explanation of this data sheet as follows.

Section: “I2C Bus Mode Control”

▪ In the explanation of the Serial Bus Interface Control Register 1

1. Delete the setting examples where the serial clock frequency exceeds 100 kHz.

2. Add the following note.

Note: This I

2C bus circuit does not support the Fast mode. It supports the Standard mode only. Although

the I

2C bus circuit itself allows the setting of a baud rate over 100 kbps, the compliance with the I2C

specification is not guaranteed in that case.

▪ In “(3) Serial clock”

1. Add the following sentence about the communication baud rate.

a. Clock source

The SCK (bits 2 to 0 in the SBICR1) is used to select a maximum transfer frequency

outputed on the SCL pin in the master mode. Set a communication baud rate that meets

the I2C bus specification, such as the shortest pulse width of tLOW, based on the equations

shown below.

In both master mode and slave mode, a pulse width of at least 4 machine cycles is require

for both “H” and “L” levels.

tLOW = 2

/fc

tHIGH = 2

/fc + 8/fc

fscl = 1/(tLow + tHIGH)

000 : Reserved

001 : Reserved

010 : 58.8

011 : 30.3

100 : 15.4

101 : 7.75

110 : 3.89

(Note)

kHz

at fc = 8MHz (Output on SCL

pin)

SCK

Serial clock selection

111 : reserved

Write-

only

TOSHIBA Microcontrollers

870 Family

(TMP87CH48U) (TMP87CH48DF) (TMP87CM48U) (TMP87CM48DF) （TMP87CH48I）

(TMP87PH48U) (TMP87PH48DF) (TMP87PM48U) (TMP87PM48DF)

TMP87PH48/PM48

2008-02-08

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