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ST10F276E Datasheet(PDF) 208 Page - STMicroelectronics

Part # ST10F276E
Description  16-bit MCU with MAC unit 832 Kbyte Flash memory and 68 Kbyte RAM
PDF  235 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10F276E Datasheet(HTML) 208 Page - STMicroelectronics

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Electrical characteristics
ST10F276E
208/235
Doc ID 12303 Rev 3
23.8.17
External memory bus timing
In the next sections the external memory bus timings are described. The given values are
computed for a maximum CPU clock of 40 MHz.
It is evident that when higher CPU clock frequency is used (up to 64 MHz), some numbers in
the timing formulas become zero or negative, which in most cases is not acceptable or
meaningful. In these cases, the speed of the bus settings tA, tC and tF must be correctly
adjusted.
Note:
All external memory bus timings and SSC timings presented in the following tables are given
by design characterization and not fully tested in production.
23.8.18
Multiplexed bus
VDD = 5V ±10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF,
ALE cycle time = 6 TCL + 2tA + tC + tF (75ns at 40 MHz CPU clock without wait states).
Table 104. Multiplexed bus
Symbol
Parameter
fCPU = 40 MHz
TCL = 12.5ns
Variable CPU clock
1/2 TCL = 1 to 64 MHz
Min.
Max.
Min.
Max.
t5
CC ALE high time
4 + tA
-
TCL - 8.5 + tA
-
ns
t6
CC Address setup to ALE
1.5 + tA
TCL - 11 + tA
ns
t7
CC Address hold after ALE
4 + tA
TCL - 8.5 + tA
ns
t8
CC
ALE falling edge to RD, WR
(with RW-delay)
4 + tA
TCL - 8.5 + tA
ns
t9
CC
ALE falling edge to RD, WR
(no RW-delay)
- 8.5 + tA
- 8.5 + tA
ns
t10
CC
Address float after RD, WR
(with RW-delay)(1)
-
6
-
6ns
t11
CC
Address float after RD, WR
(no RW-delay)(1)
18.5
TCL + 6
ns
t12
CC
RD, WR low time
(with RW-delay)
15.5 + tC
-
2TCL - 9.5 + tC
-
ns
t13
CC
RD, WR low time
(no RW-delay)
28 + tC
3TCL - 9.5 + tC
ns
t14
SR
RD to valid data in
(with RW-delay)
-
6 + tC
-
2TCL - 19 + tC
ns
t15
SR
RD to valid data in
(no RW-delay)
18.5 + tC
3TCL - 19 + tC
ns
t16
SR ALE low to valid data in
17.5 + tA + tC
3TCL - 20 + tA + tC
ns
t17
SR
Address/Unlatched CS to
valid data in
20 + 2tA + tC
4TCL - 30 + 2tA + tC ns
t18
SR
Data hold after RD
rising edge
0-
0
-
ns
t19
SR Data float after RD
-16.5 + tF
-
2TCL - 8.5 + tF
ns



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