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ST10F276E Datasheet(PDF) 214 Page - STMicroelectronics |
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ST10F276E Datasheet(HTML) 214 Page - STMicroelectronics |
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214 / 235 page  Electrical characteristics ST10F276E 214/235 Doc ID 12303 Rev 3 23.8.19 Demultiplexed bus VDD = 5V ±10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF, ALE cycle time = 4 TCL + 2tA + tC + tF (50ns at 40 MHz CPU clock without wait states). Table 105. Demultiplexed bus Symbol Parameter fCPU = 40 MHz TCL = 12.5ns Variable CPU clock 1/2 TCL = 1 to 64 MHz Min. Max. Min. Max. t5 CC ALE high time 4 + tA - TCL - 8.5 + tA -ns t6 CC Address setup to ALE 1.5 + tA - TCL - 11 + tA -ns t80 CC Address/Unlatched CS setup to RD, WR (with RW-delay) 12.5 + 2tA - 2TCL - 12.5 + 2tA -ns t81 CC Address/Unlatched CS setup to RD, WR (no RW-delay) 0.5 + 2tA - TCL - 12 + 2tA -ns t12 CC RD, WR low time (with RW-delay) 15.5 + tC - 2TCL - 9.5 + tC -ns t13 CC RD, WR low time (no RW-delay) 28 + tC - 3TCL - 9.5 + tC -ns t14 SR RD to valid data in (with RW-delay) - 6 + tC - 2TCL - 19 + tC ns t15 SR RD to valid data in (no RW-delay) - 18.5 + tC - 3TCL - 19 + tC ns t16 SR ALE low to valid data in - 17.5 + tA + tC - 3TCL - 20 + tA + tC ns t17 SR Address/Unlatched CS to valid data in - 20 + 2tA + tC - 4TCL - 30 + 2tA + tC ns t18 SR Data hold after RD rising edge 0- 0 - ns t20 SR Data float after RD rising edge (with RW-delay)(1) - 16.5 + tF - 2TCL - 8.5 + tF + 2tA ns t21 SR Data float after RD rising edge (no RW-delay)(1) - 4 + tF - TCL - 8.5 + tF + 2tA ns t22 CC Data valid to WR 10 + tC - 2TCL - 15 + tC -ns t24 CC Data hold after WR 4 + tF - TCL - 8.5 + tF -ns t26 CC ALE rising edge after RD, WR -10 + tF - -10 + tF -ns t28 CC Address/Unlatched CS hold after RD, WR (2) 0 + tF - 0 + tF -ns t28hCC Address/Unlatched CS hold after WRH - 5 + tF - - 5 + tF -ns |
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