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ST10F276E Datasheet(PDF) 215 Page - STMicroelectronics |
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ST10F276E Datasheet(HTML) 215 Page - STMicroelectronics |
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215 / 235 page  ST10F276E Electrical characteristics Doc ID 12303 Rev 3 215/235 1 Partially tested, guaranteed by design characterization. Figures 61 to 64 present the different configurations of external memory cycle for a demultiplexed bus. t38 CC ALE falling edge to Latched CS - 4 - tA 6 - tA - 4 - tA 6 - tA ns t39 SR Latched CS low to Valid Data In - 16.5 + tC + 2tA - 3TCL - 21+ tC + 2tA ns t41 CC Latched CS hold after RD, WR 2 + tF - TCL - 10.5 + tF -ns t82 CC Address setup to RdCS, WrCS (with RW-delay) 14 + 2tA - 2TCL - 11 + 2tA -ns t83 CC Address setup to RdCS, WrCS (no RW-delay) 2 + 2tA - TCL -10.5 + 2tA -ns t46 SR RdCS to Valid Data In (with RW-delay) - 4 + tC - 2TCL - 21 + tC ns t47 SR RdCS to Valid Data In (no RW-delay) - 16.5 + tC - 3TCL - 21 + tC ns t48 CC RdCS, WrCS low time (with RW-delay) 15.5 + tC - 2TCL - 9.5 + tC -ns t49 CC RdCS, WrCS low time (no RW-delay) 28 + tC - 3TCL - 9.5 + tC -ns t50 CC Data valid to WrCS 10 + tC - 2TCL - 15 + tC -ns t51 SR Data hold after RdCS 0- 0 - ns t53 SR Data float after RdCS (with RW-delay) - 16.5 + tF - 2TCL - 8.5 + tF ns t68 SR Data float after RdCS (no RW-delay) - 4 + tF - TCL - 8.5 + tF ns t55 CC Address hold after RdCS, WrCS - 8.5 + tF - - 8.5 + tF -ns t57 CC Data hold after WrCS 2 + tF - TCL - 10.5 + tF -ns 1. RW-delay and tA refer to the next following bus cycle. 2. Read data is latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address changes which occur before the end of RD have no impact on read cycles. Table 105. Demultiplexed bus (continued) Symbol Parameter fCPU = 40 MHz TCL = 12.5ns Variable CPU clock 1/2 TCL = 1 to 64 MHz Min. Max. Min. Max. |
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