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ST10F276E Datasheet(PDF) 220 Page - STMicroelectronics |
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ST10F276E Datasheet(HTML) 220 Page - STMicroelectronics |
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220 / 235 page  Electrical characteristics ST10F276E 220/235 Doc ID 12303 Rev 3 23.8.20 CLKOUT and READY VDD = 5V ±10%, VSS = 0V, TA = -40 to + 125°C, CL = 50pF Table 106. CLKOUT and READY Symbol Parameter fCPU = 40 MHz TCL = 12.5ns Variable CPU clock 1/2 TCL = 1 to 64 MHz Min. Max. Min. Max. t29 CC CLKOUT cycle time 25 25 2TCL 2TCL ns t30 CC CLKOUT high time 9 - TCL - 3.5 - ns t31 CC CLKOUT low time 10 TCL - 2.5 ns t32 CC CLKOUT rise time -4- 4 ns t33 CC CLKOUT fall time ns t34 CC CLKOUT rising edge to ALE falling edge - 2 + tA 8 + tA - 2 + tA 8 + tA ns t35 SR Synchronous READY setup time to CLKOUT 17 - 17 - ns t36 SR Synchronous READY hold time after CLKOUT 22 ns t37 SR Asynchronous READY low time 35 2TCL + 10 ns t58 SR Asynchronous READY setup time(1) 1. These timings are given for characterization purposes only, in order to assure recognition at a specific clock edge. 17 17 ns t59 SR Asynchronous READY hold time(1) 22 ns t60 SR Async. READY hold time after RD, WR high (Demultiplexed Bus)(2) 2. Demultiplexed bus is the worst case. For multiplexed bus 2TCLs must be added to the maximum values. This adds even more time for deactivating READY. 2tA and tC refer to the next following bus cycle and tF refers to the current bus cycle. 02tA + tC + tF 02tA + tC + tF ns |
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