 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ST10F276E Datasheet(PDF) 222 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ST10F276E Datasheet(HTML) 222 Page - STMicroelectronics |
|
|
222 / 235 page  Electrical characteristics ST10F276E 222/235 Doc ID 12303 Rev 3 23.8.21 External bus arbitration VDD = 5V ±10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF Figure 66. External bus arbitration (releasing the bus) 1. The ST10F276E will complete the currently running bus cycle before granting bus access. 2. This is the first possibility for BREQ to become active. 3. The CS outputs will be resistive high (pull-up) after t64. Table 107. External bus arbitration Symbol Parameter fCPU = 40 MHz TCL = 12.5ns Variable CPU Clock 1/2 TCL = 1 to 64 MHz Unit Min. Max. Min. Max. t61 SR HOLD input setup time to CLKOUT 18.5 - 18.5 - ns t62 CC CLKOUT to HLDA high or BREQ low delay - 12.5 - 12.5 t63 CC CLKOUT to HLDA low or BREQ high delay t64 CC CSx release 1 20 20 t65 CC CSx drive - 415- 415 t66 CC Other signals release 1 -20 - 20 t67 CC Other signals drive - 415- 415 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
New Zealand ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
