S29AS016J datasheet(25/60 Pages) SPANSION

25 / 60 page

February 1, 2012 S29AS016J_00_11

S29AS016J

Data

She e t

7.14

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data protection

against inadvertent writes (refer to Table 11.1 on page 36 for command definitions). In addition, the following

hardware data protection measures prevent accidental erasure or programming, which might otherwise be

caused by spurious system level signals during VCC power-up and power-down transitions, or from system

noise.

7.14.1

Low VCC Write Inhibit

When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC

power-up and power-down. The command register and all internal program/erase circuits are disabled, and

the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the

proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.

7.14.2

Write Pulse Glitch Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

7.14.3

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,

CE# and WE# must be a logical zero (VIL) while OE# is a logical one (VIH).

7.14.4

Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising

edge of WE#. The internal state machine is automatically reset to reading array data on power-up.

S29AS016J Datasheet(PDF) 25 Page - SPANSION