TS7003

TS7003DS r1p0

Page 13

RTFDS

Figure 12: SPI/MICROWIRE-TS7003 Serial Interface Timing Details with [CPOL:CPHA] = [0:0].

Figure 13: QSPI-TS7003 Serial Interface Timing Details with [CPOL:CPHA] = [0:1].

PCB Layout, Ground Plane Management, and

Capacitive Bypassing

For best performance, printed circuit boards should

always be used and wire-wrap boards are not

recommended. Good PC board layout techniques

ensure that digital and analog signal lines are kept

separate

from

each

other,

analog

and

digital

(especially clock) lines are not routed parallel to one

another, and high-speed digital lines are not routed

underneath the ADC package.

A

recommended

system

ground

connection

is

illustrated in Figure 14. A single-point analog ground

(star ground point) should be created at the A C’s

GND and separate from the logic ground. All analog

grounds as well as t

he A C’s G

pin should be

connected to the star ground. No other digital system

ground should be connected to this ground. For

lowest-noise operation, the ground return to the star

ground’s power supply should be low impedance and

as short as possible.

affect the A C’s high-speed comparator. Therefore, it

ground with 0.1μF and 1μF capacitors in parallel and

placed close to the A C’s Pin 1. Component lead

lengths should be very short for optimal supply-noise

rejection. If the power supply is very noisy, an

optional 10-

Ω resistor can be used in conjunction with

the bypass capacitors to form a low-pass filter as

shown in Figure 14.

Figure 14: Recommended Power Supply

Bypassing and Star Ground

Configuration.