S29GL01GS datasheet(65/104 Pages) SPANSION

65 / 104 page

March 16, 2012 S29GL_128S_01GS_00_06

GL-S MirrorBit® Family

Data

She e t

Hardware Interface

Signal Descriptions

7.1

Address and Data Configuration

Address and data are connected in parallel (ADP) via separate signal inputs and I/Os.

7.2

Input/Output Summary

7.3

Versatile I/O Feature

The maximum output voltage level driven by, and input levels acceptable to, the device are determined by the

VIO power supply. This supply allows the device to drive and receive signals to and from other devices on the

same bus having interface signal levels different from the device core voltage.

Table 7.1 I/O Summary

Symbol

Type

Description

RESET#

Input

Hardware Reset. At VIL, causes the device to reset control logic to its standby state, ready

for reading array data.

CE#

Input

Chip Enable. At VIL, selects the device for data transfer with the host memory controller.

OE#

Input

Output Enable. At VIL, causes outputs to be actively driven. At VIH, causes outputs to be

high impedance (High-Z).

WE#

Input

Write Enable. At VIL, indicates data transfer from host to device. At VIH, indicates data

transfer is from device to host.

AMAX-A0

Input

Address inputs.

A25-A0 for S29GL01GS

A24-A0 for S29GL512S

A23-A0 for S29GL256S

A22-A0 for S29GL128S

DQ15-DQ0

Input/Output

Data inputs and outputs

WP#

Input

Write Protect. At VIL, disables program and erase functions in the lowest or highest address

64-kword (128-kB) sector of the device. At VIH, the sector is not protected. WP# has an

internal pull up; When unconnected WP# is at VIH.

RY/BY#

Output - open drain

Ready/Busy. Indicates whether an Embedded Algorithm is in progress or complete. At VIL,

the device is actively engaged in an Embedded Algorithm such as erasing or programming.

At High-Z, the device is ready for read or a new command write - requires external pull-up

resistor to detect the High-Z state. Multiple devices may have their RY/BY# outputs tied

together to detect when all devices are ready.

VCC

Power Supply

Core power supply

VIO

Power Supply

Versatile IO power supply.

VSS

Power Supply

Power supplies ground

No Connect

Not Connected internally. The pin/ball location may be used in Printed Circuit Board (PCB)

as part of a routing channel.

RFU

No Connect

Reserved for Future Use. Not currently connected internally but the pin/ball location should

be left unconnected and unused by PCB routing channel for future compatibility. The pin/ball

may be used by a signal in the future.

DNU

Reserved

Do Not Use. Reserved for use by Spansion. The pin/ball is connected internally. The input

has an internal pull down resistance to VSS. The pin/ball can be left open or tied to VSS on

the PCB.

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