HT56R67_12 datasheet(70/104 Pages) HOLTEK

70 / 104 page

HT56R67/HT56R668/HT56C668/HT56R678/HT56C678/HT56R688

Rev. 1.60

May 21, 2012

External Peripheral Interrupt

The External Peripheral Interrupt operates in a similar

way to the external interrupt and is contained within the

Multi-function interrupt.

For an external peripheral interrupt to occur, the global

interrupt enable bit, EMI, external peripheral interrupt

enable bit, EPI, and Multi-function interrupt enable bit,

EMFI, must first be set. An actual external peripheral in-

terrupt will take place when the external interrupt re-

quest flag, PEF, is set, a situation that will occur when a

negative transition, appears on the PINT pin. The exter-

nal peripheral interrupt pin is pin-shared with one of the

segment pins, and is configured as a peripheral interrupt

pin via a configuration option. When the interrupt is en-

abled, the stack is not full and a negative transition type

appears on the external peripheral interrupt pin, a sub-

routine call to the Multi-function interrupt vector at

location18H, will take place. When the external periph-

eral interrupt is serviced, the EMI bit will be cleared to

disable other interrupts, however only the MFF interrupt

request flag will be reset. As the PEF flag will not be au-

tomatically reset, it has to be cleared by the application

program.

Timer/Event Counter Interrupt

For a Timer/Event Counter 0 or Timer/Event Counter 1

interrupt to occur, the global interrupt enable bit, EMI,

and the corresponding timer interrupt enable bit, ET0I or

ET1I must first be set. An actual Timer/Event Counter in-

terrupt will take place when the Timer/Event Counter re-

quest flag, T0F or T1F is set, a situation that will occur

when the Timer/Event Counter overflows. When the in-

terrupt is enabled, the stack is not full and a Timer/Event

Counter overflow occurs, a subroutine call to the timer

interrupt vector at location 0CH or 10C, will take place.

When the interrupt is serviced, the timer interrupt re-

quest flag, T0F or T1F, will be automatically reset and

the EMI bit will be automatically cleared to disable other

interrupts.

Timer Event Counter 0 and Timer/Event Counter 1 have

their own individual interrupt vectors, however the inter-

rupt vector for Timer/Event Counter 2 or Timer/Event

counter 3 is contained within the Multi-function Interrupt.

For a Timer/Event Counter 2 or a Timer/Event counter 3

interrupt to occur, the global interrupt enable bit, EMI,

Timer/Event Counter 2 or Timer/Event counter 3 inter-

rupt enable bit, ET2I or ET3I, and Multi-function interrupt

enable bit, EMFI, must first be set. An actual interrupt

will take place when the Timer/Event Counter 2 or

Timer/Event counter 3 request flag, T2F or T3F, is set, a

situation that will occur when the Timer/Event Counter 2

or Timer/Event counter 3 overflows. When the interrupt

is enabled, the stack is not full and the Timer/Event

Counter 2 or Timer/Event counter 3 overflows, a subrou-

tine call to the Multi-function interrupt vector at location

18H, will take place. When the Timer/Event 2 or

Timer/Event counter 3 interrupt is serviced, the EMI bit

will be cleared to disable other interrupts, however only

the MFF interrupt request flag will be reset. As the T2F

or T3F flag will not be automatically reset, it has to be

cleared by the application program.

A/D Interrupt

The A/D Interrupt is contained within the Multi-function

Interrupt.

For an A/D Interrupt to be generated, the global interrupt

enable bit, EMI, A/D Interrupt enable bit, EADI, and

Multi-function interrupt enable bit, EMFI, must first be

set. An actual A/D Interrupt will take place when the A/D

Interrupt request flag, ADF, is set, a situation that will oc-

cur when the A/D conversion process has finished.

When the interrupt is enabled, the stack is not full and

the A/D conversion process has ended, a subroutine

call to the Multi-function interrupt vector at location18H,

will take place. When the A/D Interrupt is serviced, the

EMI bit will be cleared to disable other interrupts, how-

ever only the MFF interrupt request flag will be reset. As

the ADF flag will not be automatically reset, it has to be

cleared by the application program.

I N T E D G E R e g i s t e r

I N T 0 E d g e S e l e c t

I N T 0 S 1

I N T 0 S 0

I N T 1 E d g e S e l e c t

I N T 1 S 1

I N T 1 S 0

N o t i m p l e m e n t e d , r e a d a s " 0 "

b 0

I N T 1 S 0 I N T 0 S 1 I N T 0 S 0

b 7

I N T 1 S 1

d i s a b l e

r i s i n g e d g e t r i g g e r

f a l l i n g e d g e t r i g g e r

d u a l e d g e t r i g g e r

d i s a b l e

r i s i n g e d g e t r i g g e r

f a l l i n g e d g e t r i g g e r

d u a l e d g e t r i g g e r

Interrupt Active Edge Register

- INTEDGE

HT56R67 Datasheet(PDF) 70 Page - Holtek Semiconductor Inc

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