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WM8940CGEFL/V Datasheet(PDF) 60 Page - Wolfson Microelectronics plc |
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WM8940CGEFL/V Datasheet(HTML) 60 Page - Wolfson Microelectronics plc |
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60 / 91 page ![]() WM8940 Production Data w PD, Rev 4.3, November 2011 60 The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings are shown in Table 49. MCLK (MHz) DESIRED OUTPUT (MHz) F2 (MHz) PRESCALE DIVIDE POSTSCALE DIVIDE (MCLKDIV) R N (Hex) K (Hex) 12 11.2896 90.3168 1 2 7.5264 7 86C226 12 12.2880 98.3040 1 2 8.192 8 3126E9 13 11.2896 90.3168 1 2 6.947446 6 F28BD4 13 12.2880 98.3040 1 2 7.561846 7 8FD525 14.4 11.2896 90.3168 1 2 6.272 6 45A1CA 14.4 12.2880 98.3040 1 2 6.826667 6 D3A06E 19.2 11.2896 90.3168 2 2 9.408 9 6872B0 19.2 12.2880 98.3040 2 2 10.24 A 3D70A3 19.68 11.2896 90.3168 2 2 9.178537 9 2DB492 19.68 12.2880 98.3040 2 2 9.990243 9 FD809F 19.8 11.2896 90.3168 2 2 9.122909 9 1F76F8 19.8 12.2880 98.3040 2 2 9.929697 9 EE009E 24 11.2896 90.3168 2 2 7.5264 7 86C226 24 12.2880 98.3040 2 2 8.192 8 3126E9 26 11.2896 90.3168 2 2 6.947446 6 F28BD4 26 12.2880 98.3040 2 2 7.561846 7 8FD525 27 11.2896 90.3168 2 2 6.690133 6 BOAC93 27 12.2880 98.3040 2 2 7.281778 7 482296 Table 49 PLL Frequency Examples COMPANDING The WM8940 supports A-law and -law companding on both transmit (ADC) and receive (DAC) sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate value to the DAC_COMP or ADC_COMP register bits respectively. If packed mode companding is desired the WL8 register bit is available. It will override the normal audio interface WL bits to give an 8-bit word length. Refer to Table 43 Audio Interface Control for setting the output word length. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R5 Companding control 6 DAC_LOOPBACK 0 Digital loopback function 0=No DAC loopback 1=Loopback enabled, DAC audio interface output is fed directly into ADC audio interface input. 4:3 DAC_COMP 0 DAC decompanding 00=off 01=reserved 10=µ-law 11=A-law 2:1 ADC_COMP 0 ADC companding 00=off 01=reserved 10=µ-law 11=A-law 0 ADC_LOOPBACK 0 Digital loopback function 0=No ADC loopback 1=Loopback enabled, ADC data output is fed directly into DAC data input. Table 50 Companding Control |
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