WM8215

Production Data

w

PD, Rev 4.3, September 2012

17

0

1

2

3

4

5

6

7

8

0

128

256

384

512

Gain Code (PGA[8:0])

0

0.5

1

1.5

2

2.5

3

3.5

0

128

256

384

512

Gain Code (PGA[8:0])

Max i/p Voltage

LOWREFS=0

Max i/p Voltage

LOWREFS=1

Figure 12 PGA Gain Characteristic

Figure 13 Peak Input Voltage to Match ADC Full-scale Range

ADC INPUT BLACK LEVEL ADJUST

The output from the PGA can be offset to match the full-scale range of the differential ADC (2*[VRT-

VRB]).

For negative-going input video signals, a black level (zero differential) output from the PGA should be

offset to the top of the ADC range by setting register bits PGAFS[1:0]=10. This will give an output

code of 3FF (hex) from the WM8215 for zero input. If code zero is required for zero differential input

then the INVOP bit should be set.

For positive going input signals the black level should be offset to the bottom of the ADC range by

setting PGAFS[1:0]=11. This will give an output code of 000 (hex) from the WM8215 for zero input.

Figure 14 ADC Input Black Level Adjust Settings