WM8983GEFLSLASHRV datasheet(85/124 Pages) WOLFSON

85 / 124 page

Production Data

WM8983

PD, Rev 4.3, May 2010

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Clock

Generation

Control

Sets the chip to be master over LRC and

BCLK

0=BCLK and LRC clock are inputs

(Slave mode)

1=BCLK and LRC clock are outputs

generated by the WM8983 (Master

mode)

4:2

BCLKDIV

000

Configures the BCLK and LRC output

frequency, for use when the chip is in

Master mode.

000=divide by 1 (BCLK=SYSCLK)

001=divide by 2 (BCLK=SYSCLK/2)

010=divide by 4

011=divide by 8

100=divide by 16

101=divide by 32

110=reserved

111=reserved

7:5

MCLKDIV

010

Sets the division for either the MCLK or

PLL clock output (selected by CLKSEL)

000=divide by 1

001=divide by 1.5

010=divide by 2 (LRC=SYSCLK/256)

011=divide by 3

100=divide by 4

101=divide by 6

110=divide by 8

111=divide by 12

CLKSEL

Controls the source of the clock for all

internal operation:

0=MCLK

1=PLL output

Table 56 Clock Control

The CKLSEL bit selects the internal source of the Master clock from the PLL (CLKSEL=1) or from

MCLK (CLKSEL=0). When the internal clock is switched from one source to another using the

CLKSEL bit, the clock originally selected must generate at least one falling edge after the CLKSEL

has changed for the switching of clocks to be successful. For example the sequence for switching

between the PLL and MCLK should be;

Change CLKSEL 1 -> 0

Wait for at least one falling edge from PLL generated clock

Disable the PLL (PLLEN=0)

WM8983GEFL/RV Datasheet(PDF) 85 Page - Wolfson Microelectronics plc

WM8983GEFL/RV Datasheet(HTML) 85 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL