WM8985GEFLSLASHR datasheet(81/121 Pages) WOLFSON

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Production Data

WM8985

PD, Rev 4.6, July 2009

AUDIO SAMPLE RATES

The WM8985 ADC high pass filter, ALC and DAC limiter characteristics are sample rate dependent.

SR should be set to the correct sample rate or the closest value if the actual sample rate is not

available.

If a sample rate that is not explicitly supported by the SR register settings is required then the

closest SR value to that sample rate should be chosen. The filter characteristics and the ALC attack

decay and hold times will scale appropriately.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R7 (07h)

Additional

Control

3:1

000

Approximate sample rate (configures the

coefficients for the internal digital filters):

000 = 48kHz

001 = 32kHz

010 = 24kHz

011 = 16kHz

100 = 12kHz

101 = 8kHz

110-111 = reserved

Table 45 Sample Rate Control

MASTER CLOCK AND PHASE LOCKED LOOP (PLL)

The WM8985 has an on-chip phase-locked loop (PLL) circuit that can be used to:

Generate master clocks for the WM8985 audio functions from another external clock, e.g. in

telecoms applications.

Generate and output (on pin CSB/GPIO1) a clock for another part of the system that is derived from

an existing audio master clock.

Figure 38 shows the PLL and internal clocking on the WM8985.

The PLL can be enabled or disabled by the PLLEN register bit.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R1 (01h)

Power

management 1

PLLEN

PLL enable

0 = PLL off

1 = PLL on

Table 46 PLLEN Control Bit

WM8985GEFL/R Datasheet(PDF) 81 Page - Wolfson Microelectronics plc

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