Production Data

WM9082

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PD, August 2012, Rev 4.1

9

DEVICE DESCRIPTION

INTRODUCTION

The WM9082 is a high performance sigma-delta Class D speaker driver designed for a range of high

performance, low-power audio applications. It is packaged in a 9-ball CSP.

The device comprises two digital input pins, which support the CLK and DATA inputs of the PDM

audio interface. Automatic Left/Right channel selection is provided using automatic detection of the

input configuration. The PDM audio interface also supports decoding of silent Control Codes which

can be used to configure the WM9082 or to select the low power, Standby operating state.

The WM9082 incorporates a selectable first-order high-pass filter for removing DC offsets and to help

prevent speaker damage. Input sample rates of 32kHz, 44.1kHz and 48kHz are supported.

The sigma-delta architecture of the Class D output driver provides good power efficiency and

improved EMI performance with respect to traditional PWM Class D designs.

The Class D speaker driver is powered from SPKVDD in the range 3.2V to 5.5V. The driver can

deliver 2.5W output into a 4Ω load. The WM9082 is suitable for positioning very close to the external

loudspeaker. The differential (BTL) outputs can connect directly to the loudspeaker with no other

external components required.

Short-circuit and thermal protection is also provided.

The WM9082 is supplied in a 9-ball 1.56 x 1.46mm CSP package, with 0.5mm ball pitch.

PDM AUDIO INTERFACE

The WM9082 supports a stereo PDM audio interface, comprising a CLK wire and a DATA wire. Two

channels of audio data are multiplexed on the DATA wire; the WM9082 speaker driver selects either

the Left channel data or the Right channel data depending on the hardware configuration of the

interface connection.

Each channel of PDM audio data consists of a stream of 1-bit data samples; the bit rate is 128 x fs,

where fs is the sample frequency of the received audio signal. Note that PDM is a ‘pulse density

modulation’ coding, where the signal amplitude is represented by the density of logic 1’s in any

window of consecutive data bits.

Two audio channels are interleaved on the PDM interface as illustrated in Figure 1. The Left channel

data is read at the rising edge of CLK; the Right channel data is read at the falling edge of CLK. See

“Signal Timing Requirements” for specific timing requirements.

CLK input

DATA input

(left & right channels interleaved)

L

R

L

R

L

R

Left channel input

L

L

L

Right channel input

R

R

R

Figure 1 PDM Audio Interface