PXD20 datasheet(95/130 Pages) FREESCALE

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Electrical characteristics

PXD20 Microcontroller Data Sheet, Rev. 2

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, fF),

according to the Nyquist theorem the conversion rate fC must be at least 2f0; it means that the constant time of the filter is greater

than or at least equal to twice the conversion period (TC). Again the conversion period TC is longer than the sampling time TS,

which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a

specific channel): in conclusion it is evident that the time constant of the filter RFCF is definitively much higher than the

sampling time TS, so the charge level on CS cannot be modified by the analog signal source during the time in which the

sampling switch is closed.

The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage

drop on CS; from the two charge balance equations above, it is simple to derive Equation 12 between the ideal and real sampled

voltage on CS:

Eqn. 12

From this formula, in the worst case (when VA is maximum, that is for instance 5V), assuming to accept a maximum error of

half a count, a constraint is evident on CF value:

Eqn. 13

4.16.2

ADC electrical characteristics

Table 44. ADC electrical characteristics

Symbol

Parameter

Conditions1

Value2

Unit

SpecID

Min

Typ

Max

VSSA

D Voltage on VSSA (ADC

reference) pin with re-

spect to ground (VSS)

—

–0.1

—

0.1

D15.1

VDDA

D Voltage on VDDA pin

(ADC reference) with re-

spect to ground (VSS)

—VDDE_A –0.

—VDDE_A +0.1

D15.2

VAINx

D Analog input voltage4

—VSSA –0.1

—

VDDA +0.1

D15.3

fADC

D ADC analog frequency

—

6—

MHz

D15.4

tADC_PU SR D ADC power up delay

—

1.5

µs

D15.5

tADC_S CC

T Sample time6

fADC = 32 MHz,

ADC_conf_sample_input =

0.5

—

µs

D15.6

fADC = 6 MHz,

ADC_conf_sample_input =

127

—21

tADC_C CC

T Conversion time7

fADC = 32 MHz,

ADC_conf_comp = 2

0.625

—

µs

D15.7

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2048 C

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