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RT7252B Datasheet(PDF) 13 Page - Richtek Technology Corporation

Part # RT7252B
Description  2A, 17V, 340/800kHz Synchronous Step-Down Converter
PDF  14 Pages
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Manufacturer  RICHTEK [Richtek Technology Corporation]
Direct Link  http://www.richtek.com
Logo RICHTEK - Richtek Technology Corporation

RT7252B Datasheet(HTML) 13 Page - Richtek Technology Corporation

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RT7252A/B
13
DS7252A/B-01 April 2012
www.richtek.com
©
Copyright
2012 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
For recommended operating condition specifications, the
maximum junction temperature is 125
°C. The junction to
ambient thermal resistance,
θJA, is layout dependent. For
SOP-8 (Exposed Pad) package, the thermal resistance,
θJA, is 75°C/W on a standard JEDEC 51-7 four-layer
thermal test board. The maximum power dissipation at
TA = 25
°C can be calculated by the following formula :
PD(MAX) = (125
°C − 25°C) / (75°C/W) = 1.333W for
SOP-8 (Exposed Pad) package
The maximum power dissipation depends on the operating
ambient temperature for fixed TJ(MAX) and thermal
resistance,
θJA. The derating curve in Figure 3 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Figure 3. Derating Curve of Maximum Power Dissipation
Layout Consideration
Follow the PCB layout guidelines for optimal performance
of the RT7252A/B
Keep the traces of the main current paths as short and
wide as possible.
Put the input capacitor as close as possible to the device
pins (VIN and GND).
SW node is with high frequency voltage swing and should
be kept at small area. Keep sensitive components away
from the SW node to prevent stray capacitive noise
pickup.
Place the feedback components to the FB pin as close
as possible.
The GND and Exposed Pad should be connected to a
strong ground plane for heat sinking and noise protection.
Figure 4. PCB Layout Guide
Table 3. Suggested Capacitors for CIN and COUT
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0
25
50
75
100
125
Ambient Temperature (°C)
Four-Layer PCB
VOUT
SW
VOUT
COUT
CIN
L
CBOOT
R2
R1
GND
Input capacitor must
be placed as close
to the IC as possible.
SW should be connected to
inductor by wide and short trace.
Keep sensitive components
away from this trace.
The resistor divider must be
connected as close to the
device as possible.
SW
VIN
BOOT
EN
NC
GND
FB
PGOOD
GND
2
3
4
5
6
7
8
9
Location
Component Supplier
Part No.
Capacitance (
μF)
Case Size
CIN
MURATA
GRM31CR61E106K
10
1206
CIN
TDK
C3225X5R1E106K
10
1206
CIN
TAIYO YUDEN
TMK316BJ106ML
10
1206
COUT
MURATA
GRM32ER61E226M
22
1210
COUT
MURATA
GRM21BR60J226M
22
0805
COUT
TDK
C3225X5R0J226M
22
1210
COUT
TAIYO YUDEN
EMK325BJ226MM
22
1210



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