RT8205M datasheet(21/26 Pages) RICHTEK

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RT8205L/M

DS8205L/M-05 June 2011

www.richtek.com

standby, and shutdown. It is released when both output

voltages are above 91% of the nominal regulation point.

The PGOOD goes low if either output turns off or is 15%

below its nominal regulator point.

Output Over Voltage Protection (OVP)

The output voltage can be continuously monitored for over

voltage. If the output voltage exceeds 12% of its set voltage

threshold, the over voltage protection is triggered and the

LGATEx low side gate drivers are forced high. This

activates the low side MOSFET switch, which rapidly

discharges the output capacitor and pulls the input voltage

downward.

The RT8205L/M is latched once OVP is triggered and can

only be released by toggling EN, ENTRIPx or cycling VIN.

There is a 5

μs delay built into the over voltage protection

circuit to prevent false alarm.

Note that the latching LGATEx high causes the output

voltage to dip slightly negative when energy has been

previously stored in the LC tank circuit. For loads that

cannot tolerate a negative voltage, place a power Schottky

diode across the output to act as a reverse polarity clamp.

If the over voltage condition is caused by a short in the

high side switch, completely turning on the low side

MOSFET can create an electrical short between the

battery and GND, which will blow the fuse and disconnect

the battery from the output.

Output Under Voltage Protection (UVP)

The output voltage can be continuously monitored for under

voltage protection. If the output is less than 52% of its set

voltage threshold, under voltage protection will be triggered,

and then both UGATEx and LGATEx gate drivers will be

forced low. The UVP will be ignored for at least 5ms (typ.)

after start up or a rising edge on ENTRIPx. Toggle ENTRIPx

or cycle VIN to reset the UVP fault latch and restart the

controller.

Thermal Protection

The RT8205L/M features thermal shutdown protection to

prevent overheat damage to the device. Thermal shutdown

occurs when the die temperature exceeds 150

°C. All

internal circuitry is inactive during thermal shutdown. The

RT8205L/M triggers thermal shutdown if VREGx is not

supplied from VOUTx, while the input voltage on VIN and

the drawing current from VREGx are too high. Even if

VREGx is supplied from VOUTx, large power dissipation

on automatic switches caused by overloading VREGx,

which may also result in thermal shutdown.

Discharge Mode (Soft-Discharge)

When ENTRIPx is low and a transition to standby or

shutdown mode occurs, or the output under voltage fault

latch is set, the output discharge mode will be triggered.

During discharge mode, the output capacitors' residual

charge will be discharge to GND through an internal switch.

Shutdown Mode

The RT8205L/M SMPS1, SMPS2, VREG3 and VREG5

have independent enabling control. Drive EN, ENTRIP1

and ENTRIP2 below the precise input falling edge trip level

to place the RT8205L/M in its low power shutdown state.

The RT8205L/M consumes only 20

μA of input current while

in shutdown. When shutdown mode is activated, the

reference turns off. The accurate 0.4V falling edge threshold

on the EN pin can be used to detect a specific analog

voltage level as well as to shutdown the device. Once in

shutdown, the 1V rising edge threshold activates, providing

sufficient hysteresis for most applications.

Power Up Sequencing and On/Off Controls

(ENTRIPx)

ENTRIP1 and ENTRIP2 control the SMPS power up

sequencing. When the RT8205L/M is in single channel

mode, ENTRIP1 or ENTRIP2 enables the respective

outputs when ENTRIPx voltage rises above 0.515V.

Since current source form ENTRIPx has 4700ppm/

°C

temperature slope, please make sure that ENTRIPx voltage

is high enough to enable the respective output in low

temperature application.

If ENTRIPx pin becomes higher than the enable threshold

voltage while another channel is starting up, soft-start is

postponed until the other channel's soft-start has

completed. If both ENTRIP1 and ENTRIP2 become higher

than the enable threshold voltage simultaneously (within

μs), both channels will be start up simultaneously. The

timing diagrams of the power sequence is shown below

(Figure 5).

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