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RT9014-FMPQV Datasheet(PDF) 2 Page - Richtek Technology Corporation

Part # RT9014-FMPQV
Description  Ultra Low Noise 300mA Dual LDO Regulator with POR, NMOS Driver and Requiring No Bypass Capacitor
PDF  12 Pages
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Manufacturer  RICHTEK [Richtek Technology Corporation]
Direct Link  http://www.richtek.com
Logo RICHTEK - Richtek Technology Corporation

RT9014-FMPQV Datasheet(HTML) 2 Page - Richtek Technology Corporation

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RT9014/A
2
DS9014/A-11 April 2011
www.richtek.com
Functional Pin Description
Pin No.
Pin
Name
Pin Function
RT9014-□□PQW
RT9014A-□□
1
1
VIN
Supply Input.
2
--
EN
Chip Enable (Active High).
--
2
EN1
Chip Enable 1 (Active High).
--
3
EN2
Chip Enable 2 (Active High).
3
--
NC
No Internal Connection Pin.
4
4
SW
Active high signal drives open-drain N-MOSFET.
Note that this pin is high impedance. There should be a pull low
100k
Ω resistor connected to GND when the control signal is
floating.
5
5
SET
Delay Set Input: Connect external capacitor to GND to set the
internal delay for the POR output. When left open, there is no
delay. This pin cannot be grounded.
6
6
GND
Common Ground.
7
7
DRV
Open-Drain Output: Capable of sinking 150mA.
8
8
POR
Power-On Reset Output: Open-drain output. Active low indicates
an output under-voltage condition on regulator 2.
9
9
VOUT2 Channel 2 Output Voltage
10
10
VOUT1 Channel 1 Output Voltage
11 (Exposed Pad) 11 (Exposed Pad) GND
The exposed pad must be soldered to a large PCB and
connected to GND for maximum power dissipation.
Typical Application Circuit
Pin Configurations
(TOP VIEW)
RT9014
RT9014A
9
8
7
1
2
3
4
5
10
GND
VIN
EN
SET
SW
VOUT1
VOUT2
POR
GND
DRV
NC
11
9
8
7
1
2
3
4
5
10
GND
VIN
EN1
SET
SW
VOUT1
VOUT2
POR
GND
DRV
EN2
11
EN
SW
VOUT2
VOUT1
RT9014
GND
VIN
1uF
VOUT1
1uF
VOUT2
1uF
VIN
POR
DRV
SET
Chip Enable
DRV Enable
CDELAY
100K
100k
CIN
COUT1
COUT2
EN1
SW
VOUT2
VOUT1
RT9014A
GND
VIN
1uF
VOUT1
1uF
VOUT2
1uF
VIN
POR
DRV
SET
Chip Enable
DRV Enable
CDELAY
100K
100k
CIN
COUT1
COUT2
EN2



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