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RT9986 Datasheet(PDF) 22 Page - Richtek Technology Corporation |
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RT9986 Datasheet(HTML) 22 Page - Richtek Technology Corporation |
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22 / 24 page  22 DS9986-00 May 2011 www.richtek.com RT9986 Table 2. Protection Items Protection type Threshold (typical) Refer to Electrical spec Protection methods IC Shutdown Delay time Reset method BAT UVLO BAT < 1.3V IC Shutdown. No-delay VDDM power reset or all enable pins set to low OVP VDDM > 6V Automatic reset at VDDM < 5.75V 100ms VDDM power reset or all enable pins set to low VDDM UVLO VDDM < 2.4V IC Shutdown. No-delay VDDM power reset or all enable pins set to low Current Limit N-MOSFET Current > 3A N-MOSFET off, P-MOSFET off. Automatic reset at next clock cycle. 100ms VDDM power reset or all enable pins set to low PVDD1 OVP PVDD1 > 6V N-MOSFET off, P-MOSFET off. No-delay VDDM power reset or all enable pins set to low PVDD1 UVP PVDD1 < (BAT − 0.8V) or PVDD1 < 1.28V after soft-start end. N-MOSFET off, P-MOSFET off. 100ms VDDM power reset or all enable pins set to low FB1 UVP FB1 < 0.4V after soft-start end. N-MOSFET off, P-MOSFET off. No-delay VDDM power reset or all enable pins set to low CH1 Step-Up FB1 Over Load (OL) FB1 < 0.7V IC Shutdown when OL occur each cycle until 100ms. 100ms VDDM power reset or all enable pins set to low Current Limit N-MOSFET Current > 3A N-MOSFET off, P-MOSFET off. Automatic reset at next clock cycle. 100ms VDDM power reset or all enable pins set to low PVDD2 OVP PVDD2 > 6V N-MOSFET off, P-MOSFET off. No-delay VDDM power reset or all enable pins set to low PVDD2 UVP PVDD2 < (BAT − 0.8V) or PVDD2 < 1.28V after soft-start end. N-MOSFET off, P-MOSFET off. 100ms VDDM power reset or all enable pins set to low FB2 UVP FB2 < 0.4V after soft-start end. N-MOSFET off, P-MOSFET off. No-delay VDDM power reset or all enable pins set to low CH2 Step-Up FB2 Over Load FB2 < 0.7V IC Shutdown when OL occur each cycle until 100ms. 100ms VDDM power reset or all enable pins set to low Current Limit P-MOSFET Current > 1.6A N-MOSFET off, P-MOSFET off. Automatic reset at next clock cycle. 100ms VDDM power reset or all enable pins set to low FB2 UVP FB2 < 0.4V after soft-start end. N-MOSFET off, P-MOSFET off. No-delay VDDM power reset or all enable pins set to low CH2 Step-Down FB2 Over Load FB2 < 0.7V IC Shutdown when OL occur each cycle until 100ms. 100ms VDDM power reset or all enable pins set to low To be continued |
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